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参数资料
| 型号： | LC708728V |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PDSO20 |
| 封装： | MO-150AE, SSOP-20 |
| 文件页数： | 11/31页 |
| 文件大小： | 332K |
| 代理商： | LC708728V |
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Two-Wire Control Mode
In this mode, the IC is controlled using two pins: SDIDEM and SCKDSD. The program data is input to the SDIDEM pin
and external the program data latching clock signal is input to the SCKDSD pin. Figure 16 presents an overview of the
timing.
This IC has the address 001101X (binary), which indicates that it is an audio device. Of these bits, the value of the last
address bit (shown as an X) depends on the input to the CSBIWL pin. The CSBIWL pin must be connected to either
DVDD or DVSS. In 2-wire control mode, two LC708728V chips in the same system can be controlled referencing this
addresss and using by the same control signal by setting the CSBIWL pin low on one chip and high on the other.
Since the LATI2S pin is not used in 2-wire control mode, it must be connected to either DVDD or DVSS. Note that if the
input level on the LATI2S pin goes from low to high or high to low during a control operation in 2-wire mode, the
operating mode will switch to 3-wire mode. If the LC708728V switches from 2-wire control mode to 3-wire control
mode, it will not return to 2-wire mode unless the MODE pin input is changed or power to the device is turned off.
Register Map
The LC708728V includes four 16-bit program registers. Data is transferred to these register by inputting that data from
the SDIMEM pin in either 2-wire control mode or 3-wire control mode.
No. 7236-19/31
LC708728V
SDIDEM
SCKDSD
ACK
R ADDR
ACK
DATA B15-8
STOP
START
DATA B7-0
R/W
ACK
Figure 16 Two-Wire Control Mode Timing Overview
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
M0
0
00000
UPDATEL
LAT7
LAT6
LAT5
LAT4
LAT3
LAT2
LAT1
LAT0
M1
0
00001
UPDATAR
RAT7
RAT6
RAT5
RAT4
RAT3
RAT2
RAT1
RAT0
M2
0
1
0
IW2
IW1
IW0
PWDN
DEEMPH
MUT
M3
0
1
IZD
0
BCP
REV
0
ATC
LRP
I2S
Address
Data
Table 6 Program Register Mapping
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