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参数资料
| 型号： | LC708728V |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PDSO20 |
| 封装： | MO-150AE, SSOP-20 |
| 文件页数： | 17/31页 |
| 文件大小： | 332K |
| 代理商： | LC708728V |
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Attenuator Control Mode
Control of left and right channel attenuation can be performed with just the left channel attenuation control by setting the
ATC register. That is, after the ATC register is set, the left channel attenuation data (the LAT register value) is used as
the attenuation data for both the left and right channels. The set value of the ATC register is applied starting with the first
audio sample after ATC is set.
Output Phase Inversion Mode
The phase of the output signal can be inverted by setting the REV register bit.
BCKIN Polarity Control Mode
Normally, LRCIN and DIN are sampled on the BCKIN rising edge. Thus it is desirable that LRCIN and DIN change
value on the BCKIN falling edge. This IC can be used in a system in which LRCIN and DIN change value on the BCKIN
rising edge by setting this register. If the BCP register is set to 1, the BCKIN polarity shown in figures 8 to 12 is inverted.
No. 7236-24/31
LC708728V
Register address
Bit
Symbol
Default value
Description
0011
2
ATC
0
Attenuator control mode
Interface control
0: Normal operation (The RAT value is used for right channel attenuator control.)
1: ATC enabled (The LAT value is used for right channel attenuator control.)
Table 17 Attenuator Control Mode
Register address
Bit
Symbol
Default value
Description
0011
4
REV
0
Analog output phase setting
Interface control
0: Normal phase
1: Inverted phase
Table 18 Output Phase Inversion Mode Control
Register address
Bit
Symbol
Default value
Description
0011
5
BCP
0
BCKIN polarity control
Interface control
0: Normal phase (Data is latched on the BCKIN rising edge.)
1: Inverted phase (Data is latched on the BCKIN falling edge.)
Table 19 BCKIN Polarity Control Mode
IZD Detection Mode
Applications can set whether or not auto-muting is performed when over 1024 samples of 0-valued data are input by
setting the IZD register.
Register address
Bit
Symbol
Default value
Description
0011
8
IZD
0
IZD detection control and auto-mute control
Interface control
0: IZD detection function disabled (Auto-mute disabled)
1: IZD detection function enabled (Auto-mute enabled)
Table 20 IZD Detection Mode Control
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