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参数资料
| 型号： | LC72130 |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP24 |
| 封装： | SDIP-24 |
| 文件页数： | 3/22页 |
| 文件大小： | 306K |
| 代理商： | LC72130 |
Continued from preceding page.
No. 4973-11/22
LC72130, 72130M
No.
Control block/data
Functions
Related data
DO pin control data
Data that determines the DO pin output
DOC0, DOC1, DOC2
The open state is selected after the power ON reset.
Note: 1. end-UC: Check for IF counter measurement completion
When end-UC is set and the IF counter is started (i.e., when CTE is changed
from zero to one), The DO pin automatically goes to the open state.
When the IF counter measurement completes, the DO pin goes low to indicate
the measurement completion state.
Depending on serial data I/O (CE: high) the DO pin goes to the open state.
2. Goes to the open state if the I/O pin is specified to be an output port.
Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE
high) will be open, regardless of the state of the DO control data (DOC0 to DOC2).
Also, the DO pin during a data output period (an OUT mode period with CE high)
will output the contents of the internal DO serial data in synchronization with the
CL pin signal, regardless of the state of the DO control data (DOC0 to DOC2).
Unlock detection data
Selects the phase error (E) detection width for checking PLL lock.
UL0, UL1
A phase error in excess of the specified detection width is seen as an unlocked state.
Note: In the unlocked state the DO pin goes low and the UL bit in the serial data
becomes zero.
Phase comparator
Controls the phase comparator dead zone.
control data
DZ0, DZ1
Dead zone widths: DZA < DZB < DZC < DZD
Clock time base
Setting TBC to one causes an 8 Hz, 40% duty clock time base signal to be output
TBC
from the BO1 pin. (BO1 data is invalid in this mode.)
Charge pump control data
Forcibly controls the charge pump output.
DLC
Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO
oscillator stopping, deadlock can be cleared by forcing the charge pump output to
low and setting Vtune to VCC. (This is the deadlock clearing circuit.)
(6)
(7)
(8)
(9)
(10)
UL0, UL1,
CTE,
IOC1, IOC2
DOC0,
DOC1,
DOC2
BO1
DOC2
DOC1
DOC0
DO pin state
0
Open
0
1
Low when the unlock state is detected
0
1
0
end-UC*1
0
1
Open
1
0
Open
1
0
1
The IO1 pin state*2
1
0
The IO2 pin state*2
1
Open
UL1
UL0
E detection width
Detector output
0
Stopped
Open
0
1
0
E is output directly
1
0
±0.55 s
E is extended by 1 to 2 ms
1
±1.11 s
E is extended by 1 to 2 ms
DZ1
DZ0
Dead zone mode
0
DZA
0
1
DZB
1
0
DZC
1
DZD
DLC
Charge pump output
0
Normal operation
1
Forced low
Continued on next page.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC72130-D-E | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Ammo Pack 制造商:ON Semiconductor 功能描述:FNFLD / PLL FREQUENCY SYNTHESIZER |
| LC72130-E | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LC72130M | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer |
| LC72131 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer |
| LC72131D | 制造商:Panasonic Industrial Company 功能描述:IC |
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