参数资料
型号: LC75806PT-H
厂商: ON Semiconductor
文件页数: 2/35页
文件大小: 0K
描述: IC LCD DISPL DVR KEY-INP 100TQFP
标准包装: 90
系列: *
LC75806PT
Specifications
Absolute Maximum Ratings at Ta = 25 ° C, VSS = 0V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN1
VIN2
VOUT1
VOUT2
IOUT1
IOUT2
IOUT3
IOUT4
Pd max
Topr
Tstg
Conditions
VDD
CE, CL, DI, RES
OSC, TEST, VDD1, VDD2, KI1 to KI5
DO
OSC, S1 to S77, COM1 to COM4, KS1 to KS6, P1 to P9
S1 to S77
COM1 to COM4
KS1 to KS6
P1 to P9
Ta=85 ° C
Ratings
-0.3 to +7.0
-0.3 to +7.0
-0.3 to VDD+0.3
-0.3 to +7.0
-0.3 to VDD+0.3
300
3
1
5
200
-40 to +85
-55 to +125
Unit
V
V
V
μ A
mA
mW
° C
° C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85 ° C, VSS = 0V
Ratings
Parameter
Supply voltage
Symbol
VDD
VDD
Conditions
min
4.5
typ
max
6.0
Unit
V
Input voltage
Input high level voltage
*1
VDD1
VDD2
VIH1
VIH2
VDD1
VDD2
CE, CL, DI, RES
KI1 to KI5
0.4VDD
0.6VDD
2/3VDD0
1/3VDD0
VDD0
VDD0
6.0
VDD
V
V
VIH3
OSC: External clock operating mode
0.4VDD
VDD
Input low level voltage
VIL1
CE, CL, DI, RES
0
0.2VDD
VIL2
VIL3
KI1 to KI5
OSC: External clock operating mode
0
0
0.2VDD
0.2VDD
V
Recommended external
resistor for RC oscillation
Recommended external
capacitor for RC oscillation
ROSC
COSC
OSC: RC oscillation operating mode
OSC: RC oscillation operating mode
39
1000
k Ω
pF
Guaranteed range of RC oscillation
External clock operating frequency
External clock duty cycle
fOSC
fCK
DCK
OSC: RC oscillation operating mode
OSC: External clock operating mode
[Figure4]
OSC: External clock operating mode
[Figure4]
19
10
30
38
38
50
76
76
70
kHz
kHz
%
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
Fall time
tds
tdh
tcp
tcs
tch
t φ H
t φ L
tr
tf
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
CL
CE, CL, DI
CE, CL, DI
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
[Figure2], [Figure3]
160
160
160
160
160
160
160
160
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
DO output deley time
DO rise time
tdc
tdr
DO RPU=4.7k Ω CL=10pF *2
[Figure2], [Figure3]
DO RPU=4.7k Ω CL=10pF *2
[Figure2], [Figure3]
1.5
1.5
μ s
μ s
Note:
* 1. VDD0=0.70VDD to VDD
* 2. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistorRPU and the load
capacitance CL.
No.A1425-2/35
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