参数资料
型号: LC75806PT-H
厂商: ON Semiconductor
文件页数: 24/35页
文件大小: 0K
描述: IC LCD DISPL DVR KEY-INP 100TQFP
标准包装: 90
系列: *
LC75806PT
? 1/3 duty
t1
t2
VDD
CE
D1 to D78
VDET
Display and control data transfer
VIL1
VDET
Internal data OC, PC90, PC91, S0, S1,
Undefined
Defined
Undefined
K0, K1, P0 to P3, SC, KSC
Internal data D79 to D153,
Undefined
Defined
Undefined
FC0 to FC2, CT0 to CT2
Internal data (D154 to D231)
Undefined
Defined
Undefined
System reset period
Note: t1 ≥ 1 [ms](Power supply voltage VDD rise time)
t2 ≥ 1 [ms](Power supply voltage VDD fall time)
[Figure 6]
(2) Reset method by the RES pin
When power is applied, a system reset is applied by setting the RES pin low level. The reset is cleared by setting the
RES pin high level after all the serial data (1/4 duty: the display data D1 to D304 and the control data, 1/3 duty: the
display data D1 to D231 and the control data) has been transferred.
In the allowable operating range (VDD=4.5 to 6.0V), A reset is applied by setting the RES pin low level.
and the reset is cleared by setting the RES pin high level.
2. Internal block states during the reset period
? CLOCK GENERATOR
A reset is applied and either the OSC pin oscillator is stopped or external clock reception is stopped
? COMMON DRIVER, SEGMENT DRIVER & LATCH
A reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
? CONTRAST ADJUSTER
A reset is applied and the display contrast adjustment circuit operation is disabled.
? KEY SCAN
A reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
? KEY BUFFER
A reset is applied and all the key data is set to low.
? GENERAL PURPOSE PORT
A reset is applied, the circuit is set to the initial state.
? CCB INTERFACE, SHIFT REGISTER, CONTROL REGISTER
Since serial data transfer is possible, these circuits are not reset.
No.A1425-24/35
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