参数资料
型号: LC75806PT-H
厂商: ON Semiconductor
文件页数: 23/35页
文件大小: 0K
描述: IC LCD DISPL DVR KEY-INP 100TQFP
标准包装: 90
系列: *
LC75806PT
Clock Signal Output Waveform
Control data
PC90
0
PC91
1
The state of P9/S77 output pin
Clock output port (P9) (Clock frequency is fOSC/2 or fCK/2)
P9
Tc/2
Tc=
1
fc
Tc
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when power is first applied and when the voltage drops, i.e.,
when the power supply voltage is less than or equal to the power down detection voltage VDET, which is 2.3V, typical.
To assure that this function operates reliably, a capacitor must be added to the power supply line so that the power
supply voltage VDD rise time when the power is first applied and the power supply voltage VDD fall time when the
voltage drops are both at least 1ms. (See Figure 5 and Figure 6.)
System Reset
The LC75806PT supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, all the key data is reset to low, and the general-purpose output ports are fixed at the low level (The
S1/P1 to S8/P8 pins are forcibly set to the segment output port function and fixed at the low level. The P9/S77 pin is
forcibly set to the general-purpose output port function and fixed at the low level). When the reset is cleared, display is
turned on, key scanning is enabled and the general-purpose output ports state setting is enabled.
1. Reset methods
(1) Reset method by the voltage detection type reset circuit (VDET)
If at least 1ms is assured as the supply voltage VDD rise time when power is applied, a system reset will be applied
by the VDET output signal when the supply voltage is brought up. If at least 1 ms is assured as the supply voltage
VDD fall time when power drops, a system reset will be applied in the same manner by the VDET output signal
when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (1/4 duty: the
display data D1 to D304 and the control data, 1/3 duty: the display data D1 to D231 and the control data) has been
transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has
been transferred. (See Figure 5 and Figure 6.)
? 1/4 duty
VDD
CE
D1 to D76
t1
VDET
Display and control data transfer
VIL1
t2
VDET
Internal data OC, PC90, PC91, S0, S1,
Undefined
Defined
Undefined
K0, K1, P0 to P3, SC, KSC
Internal data D77 to D152,
Undefined
Defined
Undefined
FC0 to FC2, CT0 to CT2
Internal data (D153 to D228)
Internal data (D229 to D304)
Undefined
Undefined
Defined
Defined
Undefined
Undefined
System reset period
Note: t1 ≥ 1 [ms](Power supply voltage VDD rise time)
t2 ≥ 1 [ms](Power supply voltage VDD fall time)
[Figure 5]
No.A1425-23/35
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