参数资料
| 型号： | LC75808W-E |
| 厂商： | ON Semiconductor |
| 文件页数： | 2/38页 |
| 文件大小： | 0K |
| 描述： | IC LCD DISPLAY DRIVER 100SQFP |
| 标准包装： | 60 |
| 系列： | * |
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LC75808W
Specifications
Absolute Maximum Ratings at Ta = 25 ° C, VSS = 0V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VLCD max
VIN1
VIN2
VIN3
VOUT1
VOUT2
VOUT3
IOUT1
IOUT2
IOUT3
IOUT4
Pd max
Topr
Tstg
Conditions
VDD
VLCD
CE, CL, DI, INH
OSC, KI1 to KI5, TEST
VLCD1, VLCD2, VLCD3, VLCD4
DO
OSC, KS1 to KS6, P1 to P4
VLCD0, S1 to S60, COM1 to COM10
S1 to S60
COM1 to COM10
KS1 to KS6
P1 to P4
Ta=85 ° C
Ratings
-0.3 to +7.0
-0.3 to +12.0
-0.3 to +7.0
-0.3 to VDD+0.3
-0.3 to VLCD+0.3
-0.3 to +7.0
-0.3 to VDD+0.3
-0.3 to VLCD+0.3
300
3
1
5
200
-40 to +85
-55 to +125
Unit
V
V
V
μ A
mA
mW
° C
° C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85 ° C, VSS = 0V
Parameter
Supply voltage
Symbol
VDD
VDD
Conditions
min
4.5
Ratings
typ
max
6.0
unit
VLCD
VLCD
VLCD, When the display contrast adjustment
circuit is used
VLCD , When the display contrast adjustment
circuit is not used
7.0
4.5
11.0
11.0
V
Output voltage
Input voltage
VLCD0
VLCD1
VLCD2
VLCD0
VLCD1
VLCD2
VLCD4
+4.5
3/4(VLCD0
-VLCD4)
2/4(VLCD0
-VLCD4)
VLCD
VLCD0
VLCD0
V
V
VLCD3
VLCD4
VLCD3
VLCD4
0
1/4(VLCD0
-VLCD4)
VLCD0
1.5
Input high level voltage
Input low level voltage
Recommended external resistance
Recommended external
capacitance
VIH1
VIH2
VIL
ROSC
COSC
CE, CL, DI, INH
KI1 to KI5
CE, CL, DI, INH, KI1 to KI5
OSC
OSC
0.8VDD
0.6VDD
0
43
680
6.0
VDD
0.2VDD
V
V
V
k Ω
pF
Guaranteed oscillation range
fOSC
OSC
25
50
100
kHz
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
DO output delay time
DO rise time
tds
tdh
tcp
tcs
tch
t φ H
t φ L
tdc
tdr
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
CL
DO RPU=4.7k Ω , CL=10pF *1
DO RPU=4.7k Ω , CL=10pF *1
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
160
160
160
160
160
160
160
1.5
1.5
ns
ns
ns
ns
ns
ns
ns
μ s
μ s
Note: * 1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the
load capacitance CL.
No.6370-2/38
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