参数资料
型号: LCMXO1200C-5FTN256C
厂商: Lattice Semiconductor Corporation
文件页数: 17/88页
文件大小: 0K
描述: IC PLD 1200LUTS 211I/O 256-BGA
标准包装: 90
系列: MachXO
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 3.6ns
电压电源 - 内部: 1.71 V ~ 3.465 V
宏单元数: 600
输入/输出数: 211
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-FTBGA(17x17)
包装: 托盘
其它名称: 220-1180
Architecture
MachXO Family Data Sheet
PIO Groups
On the MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells
and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO
groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respective
sysIO buffers and PADs.
On all MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/O
pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins.
The MachXO1200 and MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger
devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these
devices can be configured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI
support.
Figure 2-15. Group of Four Programmable I/O Cells
This structure is used on the
left and right of MachXO devices
PIO A
PIO B
Four PIOs
PIO C
PIO D
Figure 2-16. Group oftSix Programmable I/O Cells
This structure is used on the top
and bottom of MachXO devices
PIO A
PIO B
PIO C
Six PIOs
PIO D
PIO E
PIO F
PADA "T"
PADB "C"
PADC "T"
PADD "C"
PADA "T"
PADB "C"
PADC "T"
PADD "C"
PADE "T"
PADF "C"
PIO
The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks
receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast
2-14
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