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参数资料
| 型号： | LCMXO1200E-5TN144C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 25/88页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.2KLUTS 144TQFP |
| 标准包装： | 60 |
| 系列： | MachXO |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 3.6ns |
| 电压电源 - 内部： | 1.14 V ~ 1.26 V |
| 宏单元数： | 600 |
| 输入/输出数： | 113 |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-TQFP（20x20） |
| 包装： | 托盘 |
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Architecture
MachXO Family Data Sheet
Device Configuration
All MachXO devices contain a test access port that can be used for device configuration and programming.
The non-volatile memory in the MachXO can be configured in two different modes:
? In IEEE 1532 mode via the IEEE 1149.1 port. In this mode, the device is off-line and I/Os are controlled by
BSCAN registers.
? In background mode via the IEEE 1149.1 port. This allows the device to remain operational in user mode
while reprogramming takes place.
The SRAM configuration memory can be configured in three different ways:
? At power-up via the on-chip non-volatile memory.
? After a refresh command is issued via the IEEE 1149.1 port.
? In IEEE 1532 mode via the IEEE 1149.1 port.
Figure 2-22 provides a pictorial representation of the different programming modes available in the MachXO
devices. On power-up, the SRAM is ready to be configured with IEEE 1149.1 serial TAP port using IEEE 1532 pro-
tocols.
Leave Alone I/O
When using IEEE 1532 mode for non-volatile memory programming, SRAM configuration, or issuing a refresh
command, users may specify I/Os as high, low, tristated or held at current value. This provides excellent flexibility
for implementing systems where reconfiguration or reprogramming occurs on-the-fly.
TransFR (Transparent Field Reconfiguration)
TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting
system operation using a single ispVM command. See TN1087, Minimizing System Interruption During Configura-
tion Using TransFR Technology for details.
Security
The MachXO devices contain security bits that, when set, prevent the readback of the SRAM configuration and
non-volatile memory spaces. Once set, the only way to clear the security bits is to erase the memory space.
For more information on device configuration, please see details of additional technical documentation at the end
of this data sheet.
2-22
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相关代理商/技术参数 |
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| LCMXO1200LUTSC-3FT256C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:MachXO Family Data Sheet |
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