参数资料
型号: LCMXO1200E-5TN144C
厂商: Lattice Semiconductor Corporation
文件页数: 88/88页
文件大小: 0K
描述: IC FPGA 1.2KLUTS 144TQFP
标准包装: 60
系列: MachXO
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 3.6ns
电压电源 - 内部: 1.14 V ~ 1.26 V
宏单元数: 600
输入/输出数: 113
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
包装: 托盘
Revision History
MachXO Family Data Sheet
Date
November 2006
Version
02.3
Section
DC and Switching
Characteristics
Change Summary
Corrections to MachXO “C” Sleep Mode Timing table - value for
t WSLEEPN (400ns) changed from max. to min. Value for t WAWAKE
(100ns) changed from min. to max.
Added Flash Download Time table.
December 2006
February 2007
August 2007
02.4
02.5
02.6
Architecture
Pinout Information
Architecture
DC and Switching
EBR Asynchronous Reset section added.
Power Supply and NC table: Pin/Ball orientation footnotes added.
Updated EBR Asynchronous Reset section.
Updated sysIO Single-Ended DC Electrical Characteristics table.
Characteristics
November 2007
02.7
DC and Switching
Added JTAG Port Timing Waveforms diagram.
Characteristics
Pinout Information
Supplemental
Information
Added Thermal Management text section.
Updated title list.
June 2009
02.8
Introduction
Added 0.8-mm 256-pin caBGA package to MachXO Family Selection
Guide table.
Pinout Information
Ordering Information
Added Logic Signal Connections table for 0.8-mm 256-pin caBGA pack-
age.
Updated Part Number Description diagram and Ordering Part Number
tables with 0.8-mm 256-pin caBGA package information.
July 2010
02.9
DC and Switching
Updated sysCLOCK PLL Timing table.
Characteristics
June 2013
03.0
All
Architecture
Updated document with new corporate logo.
Architecture Overview – Added information on the state of the
register on power up and after configuration.
DC and Switching
Characteristics
MachXO1200 and MachXO2280 Hot Socketing Specifications table –
Removed footnote 4.
Added MachXO Programming/Erase Specifications table.
7-3
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