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参数资料
型号： LFEC1E-3TN100C
厂商： Lattice Semiconductor Corporation
文件页数： 129/163页
文件大小： 0K
描述： IC FPGA 1.5KLUTS 67I/O 100-TQFP
标准包装： 90
系列： EC
逻辑元件/单元数： 1500
RAM 位总计： 18432
输入/输出数： 67
电源电压： 1.14 V ~ 1.26 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 100-LQFP
供应商设备封装： 100-TQFP（14x14）
其它名称： 220-1233
4-2
Pinout Information
LatticeECP/EC Family Data Sheet
TDI
I
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
TDO
O
Output pin. Test Data out pin used to shift data out of device using 1149.1.
VCCJ
—VCCJ - The power supply pin for JTAG Test Access Port.
Configuration Pads (used during sysCONFIG)
CFG[2:0]
I
Mode pins used to specify configuration modes values latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
INITN
I/O
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
PROGRAMN
I
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
DONE
I/O
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
CCLK
I/O
Configuration Clock for configuring an FPGA in sysCONFIG mode.
BUSY/SISPI
I/O
Read control command in SPI3 or SPIX mode.
CSN
I
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
CS1N
I
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
WRITEN
I
Write Data on Parallel port (Active low).
D[7:0]/SPID[0:7]
I/O
sysCONFIG Port Data I/O.
DOUT/CSON
O
Output for serial configuration data (rising edge of CCLK) when using sys-
CONFIG port.
DI/CSSPIN
I/O
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled. Output when used in
SPI/SPIX modes.
Signal Descriptions (Cont.)
Signal Name
I/O
Description
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相关代理商/技术参数
参数描述
LFEC1E-3TN100I 功能描述:FPGA - 现场可编程门阵列 1.5K LUTs 67 I/O 1.2V -3 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFEC1E-3TN144C 功能描述:FPGA - 现场可编程门阵列 1.5K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFEC1E-3TN144I 功能描述:FPGA - 现场可编程门阵列 1.5K LUTs 97 I/O 1.2V -3 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFEC1E-4F256C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC1E-4F256I 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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