收藏本站
参数资料
型号： LFEC1E-3TN100C
厂商： Lattice Semiconductor Corporation
文件页数： 79/163页
文件大小： 0K
描述： IC FPGA 1.5KLUTS 67I/O 100-TQFP
标准包装： 90
系列： EC
逻辑元件/单元数： 1500
RAM 位总计： 18432
输入/输出数： 67
电源电压： 1.14 V ~ 1.26 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 100-LQFP
供应商设备封装： 100-TQFP（14x14）
其它名称： 220-1233
2-19
Architecture
LatticeECP/EC Family Data Sheet
Signed and Unsigned with Different Widths
The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For
unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36
width is reached. Table 2-8 provides an example of this.
Table 2-8. An Example of Sign Extension
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two
unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and
overflow signal is indicated. When two positive numbers are added with a negative sum and when two negative
numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and an overflow
signal is indicated. Note when overflow occurs the overflow flag is present for only one cycle. By counting these
overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow signals for signed
and unsigned operands are listed in Figure 2-23.
Figure 2-23. Accumulator Overflow/Underflow Conditions
Number Unsigned
Unsigned
9-bit
Unsigned
18-bit
Signed
Two’s Complement
Signed 9-Bits
Two’s Complement
Signed 18-bits
+5
0101
000000101
000000000000000101
0101
000000101
000000000000000101
-6
0110
000000110
000000000000000110
1010
111111010
111111111111111010
000000000
000000001
000000010
000000011
111111101
111111110
111111111
Overflow signal is generated
for one cycle when this
boundary is crossed
0
+1
+2
+3
-3
-2
-1
Unsigned Operation
Signed Operation
0101111111
0101111110
0101111101
0101111100
1010000010
1010000001
1010000000
255
254
253
252
254
255
256
000000000
000000001
000000010
000000011
111111101
111111110
111111111
Carry signal is generated for
one cycle when this
boundary is crossed
0
1
2
3
509
510
511
0101111111
0101111110
0101111101
0101111100
1010000010
1010000001
1010000000
255
254
253
252
258
257
256
相关PDF资料
PDF描述
VE-B21-CW CONVERTER MOD DC/DC 12V 100W
HMC36DREH-S93 CONN EDGECARD 72POS .100 EYELET
VI-2NX-EU CONVERTER MOD DC/DC 5.2V 200W
VI-2NF-EU CONVERTER MOD DC/DC 72V 200W
AIML-0805-R18K-T INDUCTOR MULTILAYER 0.18UH 0805
相关代理商/技术参数
参数描述
LFEC1E-3TN100I 功能描述:FPGA - 现场可编程门阵列 1.5K LUTs 67 I/O 1.2V -3 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFEC1E-3TN144C 功能描述:FPGA - 现场可编程门阵列 1.5K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFEC1E-3TN144I 功能描述:FPGA - 现场可编程门阵列 1.5K LUTs 97 I/O 1.2V -3 Speed IND RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFEC1E-4F256C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC1E-4F256I 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*