参数资料
型号: LFXP10C-L-EV
厂商: Lattice Semiconductor Corporation
文件页数: 4/20页
文件大小: 0K
描述: BOARD EVAL LATTICEXP10C STD
标准包装: 1
系列: XP
类型: FPGA
适用于相关产品: LFXP10C
所含物品:
其它名称: LFXP10CLEV
LatticeXP Standard Evaluation Board
Lattice Semiconductor
Figure 2. Core Voltage Select Jumpers
JP4
JP5
JP6
1.2 V
ADJ
3.3 V
User’s Guide
VCC_CORE
The LatticeXP device has eight sysIO? buffer banks; each is capable of supporting multiple I/O standards. Each
sysIO bank has its own I/O supply voltage (VCCIO) and two voltage reference resources, VREF1 and VREF2, that
allow each bank to be completely independent from the others.
Please refer to the LatticeXP Family Data Sheet for additional information about supported I/O standards. This data
sheet can be downloaded from www.latticesemi.com.
The LatticeXP Standard Evaluation Board provides individual control of each I/O bank capable of supporting
VCCIO between 1.2V and 3.3V. The board provides jumper blocks which allow the end user to select 1.2V, 3.3V or
an adjustable voltage between these two voltages. Figure 3 shows a typical layout for a VCCIO select jumper block.
Table 1 details the VCCIO bank selection connectors.
Figure 3. VCCIO Jumper Block
VCCIO
Table 1. VCCIO Connectors
VCCIO Bank
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
Connector Number
JP1
JP2
JP3
JP10
JP11
JP12
JP13
JP14
Device Clocks
The LatticeXP Standard Evaluation Board provides a variety of ways to input clock signals to the LatticeXP device.
These include an on-board crystal oscillator, SMA connectors and 0.1” header pins. Clock inputs connect to pri-
4
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