参数资料
型号: LFXP10C-L-EV
厂商: Lattice Semiconductor Corporation
文件页数: 8/20页
文件大小: 0K
描述: BOARD EVAL LATTICEXP10C STD
标准包装: 1
系列: XP
类型: FPGA
适用于相关产品: LFXP10C
所含物品:
其它名称: LFXP10CLEV
LatticeXP Standard Evaluation Board
Lattice Semiconductor
User’s Guide
Device I/O Banks 2 and 3
I/O banks 2 and 3 contain general purpose I/Os with LVDS transmit/receive pairs. These I/O pairs are connected to
two 0.1” headers suitable for connecting to a logic analyzer or ribbon cable. Table 4 details the I/O banks 2 and 3
connections.
Table 4. Banks 2 and 3 I/O Connections
LatticeXP-10 Pin Number
Connection
I/O Bank
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
Positive
C15
E14
E15
C16
F13
F16
G14
H14
H12
H16
G13
J14
K16
K13
K15
N16
L14
L13
N14
R16
N15
L12
Negative 1
D15
F14
F15
B16
G12
G16
G15
H15
H13
J16
J15
L16
K12
K14
M16
L15
M14
M15
P16
P15
Positive
J24-3
J24-1
J24-19
J24-5
J24-17
J24-7
J24-13
J24-21
J24-15
J24-9
J24-25
J23-1
J23-3
J23-13
J23-5
J23-15
J23-7
J23-9
J23-21
J23-19
J23-17
SW4
Negative 1
J24-4
J24-2
J24-20
J24-6
J24-18
J24-8
J24-14
J24-22
J24-16
J24-10
J23-2
J23-4
J23-14
J23-6
J23-16
J23-8
J23-10
J23-22
J23-20
J23-18
1. Blank cell indicated pin with no negative paired pin.
Each I/O pair is connected to a resistor termination network, and the trace lengths are matched. Figure 5 shows
the termination network for these differential pairs. These resistors are not installed, and the series resistors use a
trace between the resistor pads. This trace can be cut to allow the installation of a series termination resistor. The
series resistors are 0805 size and the parallel resistors are 0603 size. Figure 5 shows this trace in relation to the
resistor pads.
Figure 5. Differential I/O Termination Network
XP-10 A Pad
Connector
XP-10 B Pad
8
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