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参数资料
| 型号： | LFXP10C-L-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL LATTICEXP10C STD |
| 标准包装： | 1 |
| 系列： | XP |
| 类型： | FPGA |
| 适用于相关产品： | LFXP10C |
| 所含物品： | 板 |
| 其它名称： | LFXP10CLEV |
LatticeXP Standard Evaluation Board
Lattice Semiconductor
User’s Guide
mary clock inputs and device PLL inputs. Clock outputs connect to PLL outputs and external feedback pins. Table
describes the clock connections to the LatticeXP device.
Table 2. Lattice XP-10 Clock Pins and Connections
On-Board OSC.
XP-10 Pin Number
N16
M16
L13
M14
N15
P15
F16
G16
F13
G12
C15
D15
M1
M2
K4
K5
L5
M6
G3
G2
E3
F4
D2
D3
A7
A8
H16
J16
T10
T11
K1
K2
XP Pin Label
RLM0_PLLT_IN_A
RLM0_PLLC_IN_A
RLM0_PLLT_OUT_A
RLM0_PLLC_OUT_A
RLM0_PLLT_FB_A
RLM0_PLLC_FB_A
RUM0_PLLT_IN_A
RUM0_PLLC_IN_A
RUM0_PLLT_OUT_A
RUM0_PLLC_OUT_A
RUM0_PLLT_FB_A
RUM0_PLLC_FB_A
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_OUT_A
LLM0_PLLC_OUT_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_OUT_A
LUM0_PLLC_OUT_A
LUM0_PLLT_FB_A
LUM0_PLLC_FB_A
PCLKT0_0
PCLKC0_0
PCLKT2_0
PCLKC2_0
PCLKT4_0
PCLKC4_0
PCLKT6_0
PCLKC6_0
PCB Connection 1
J23-15
J23-16
J23-9
J23-10
J23-17
J23-18
J24-7
J24-8
J24-17
J24-18
J24-3
J-24-4
SMA J12
SMA J14
SMA J16
SMA J18
SMA J20
SMA J22
SMA J19
SMA J21
SMA J15
SMA J17
SMA J7
SMA J9
OSC
Test Point
J24-9
J24-10
Test Pad
Test Pad
SMA J8
SMA J10
Resistor 2
R89
N/A
N/A
N/A
N/A
N/A
R90
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
R104
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Buffered (Y/N) 3
Y
N
N
N
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
1. Check the schematic pages for termination resistors connected to these pins.
2. 0_ resistor connecting to on-board oscillator.
3. Indicates a non-inverting buffer between the oscillator and pin.
The oscillator socket accepts both full-size and half-size oscillators and can route to different clock inputs, depend-
ing on installation of several 0 Ω resistors. The oscillator has a 22 Ω series termination resistor at the oscillator out-
put. These inputs correspond with PCLKT0, RLM0_PLLT_IN_A and RUM0_PLLT_IN_A. The oscillator supply
voltage is changeable, via the VCC_OSC header, located at JP9. The onboard oscillator operates at 3.3V. It is pos-
sible to power this socket from the following supplies: 3.3V, VCCIO0, VCCIO2 or VCCIO3, depending on the I/O
bank being used and the operating conditions for the chosen oscillator.
5
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