参数资料
型号: LFXP10C-L-EV
厂商: Lattice Semiconductor Corporation
文件页数: 9/20页
文件大小: 0K
描述: BOARD EVAL LATTICEXP10C STD
标准包装: 1
系列: XP
类型: FPGA
适用于相关产品: LFXP10C
所含物品:
其它名称: LFXP10CLEV
LatticeXP Standard Evaluation Board
Lattice Semiconductor
User’s Guide
Figure 6. Close-up of Series/Passthrough
Resistor Pads
C u t trace to
install resistor
Device I/O Banks 4 and 5
I/O banks 4 and 5 consist of general purpose I/O pins. These pins connect to test pads on the board. The test pads
are paired with a ground pad, which are spaced on 0.1” centers. In addition to the test pads, these I/O banks are
connected to a pull-up, pull-down and series resistor network. The resistor network is not populated. The series
resistors are 0805 size, and the pull-up/pull-down resistors are 0603 size. Figure 7 shows the schematic for the
individual I/O termination network.
Table 5. Banks 4 and 5 I/O Connections
Position
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Pin Number
T3
R3
N5
R4
T5
P6
N6
M7
N7
M8
R8
T9
T7
R7
T11
T10
P13
R13
M11
N11
R10
P10
R12
T12
T15
R15
GND Row
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number
P5
R1
R2
T2
R5
T4
T6
R6
T8
P8
N8
P7
R9
P9
N9
M9
T13
P14
N10
M10
P11
N12
R11
P12
T14
R14
GND Row
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
9
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