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参数资料
| 型号： | LM1253AAE/NA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 画面叠加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDIP28 |
| 封装： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件页数： | 11/61页 |
| 文件大小： | 1671K |
| 代理商： | LM1253AAE/NA |
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Pre-Amp Functional Description
(Continued)
Active Video Transfer Characteristic
Gain, contrast, and DC Offset control the amplitude of the
active video. The Contrast Control range is 20 dB (10X) and
the Gain Control range is 10 dB (3.2X). The DC offset can
vary the active video output level by about 470 mV in total,
allowing a total range of adjustment of about 24V in seven
3.4V steps at the output of a typical LM2453 CRT driver.
OSD Transfer Characteristic
Gain, DC Offset, and OSD Contrast control the amplitude of
the OSD signal. The OSD is not affected by the Brightness
control, but is proportional to the Gain control, with a gain
control range of 10 dB (3.2X). The DC offset will affect the
OSD output level by 470 mV in total. The OSD Contrast will
change the amplitude of the OSD output level by 610 mV in
total.
Brightness/Bias Transfer Characteristic
Bias, Brightness, Gain, and Pedestal control the amplitude
of the brightness/bias (clamp) portion of the signal. The bias
control range sets the brightness/bias pulse between 0.12V
and 0.55V below the value of V
REF during blanking. The bias
voltage is unaffected by changes in the other controls. The
brightness control is bi-directional and adds or subtracts an
additional amount of between –0.2V and +0.2V to the
brightness/bias pulse during blanking, when gain is set to
maximum. If gain is reduced, the brightness output voltage is
reduced in proportion to allow gain tracking of the brightness
control. The Pedestal controls the offset to the brightness
control, in order that bi-directional operation of the bright-
ness control is always possible at all bias voltage settings.
Auto Beam Limit Control
The Auto Beam Limit control reduces the gain of the video
amplifier in response to a control voltage proportional to the
CRT beam current. It is not recommended that this input be
used as an analog contrast control.
Horizontal Phase Locked Loop
A phase locked oscillator produces a pixel clock for the OSD
generator. This oscillator takes the HBLANK signal as the
sync signal. A programmable divider sets the divide ratio and
thus the number of pixels on a horizontal line.
Fault Operation
Loss of Vertical Flyback Pulse
Loss of vertical flyback pulse implies that the monitor is not
scanning, and therefore no image is being displayed. The
VBLANK pulses are still required by the LM2453 CRT driver
in order to maintain correct bias conditions in the CRT until
the power supplies are switched off, but video is set at black
level.
Note also that interlace mode is supported by the LM1253A.
In interlace mode, a frame is composed of two sequential
fields. In the first field, the odd lines are displayed. In the
second field the even lines are displayed. A complete frame
consists of an odd number of horizontal lines, so that each
field contains a half line. This will result in an alternate half
line phase difference between each field of the VFLYBACK
pulse with respect to the HBLANK pulse.
Loss of Horizontal Flyback
Loss of horizontal flyback pulse implies that the monitor is
not scanning, and therefore no image is being displayed.
The HBLANK pulse is still required by the LM2453 CRT
driver in order to maintain correct bias conditions in the CRT
until the power supplies are switched off, but video is set at
black level.
In the absence of an externally supplied horizontal flyback
pulse, the PLL will free run and generate its own HBLANK
pulse. The PLL free run pulse will be gated into the HBLANK
line to the pre-amp to allow normal operation of the pre-amp
and driver biasing.
V
CC Detect
The V
CC power supply will be continuously monitored by the
LM1253A. Should the V
CC supply drop to less than VCCDET
then the video signal will be set to V
REF.
The device will continue to operate down to V
CCDET, al-
though some parameters may fall outside of specification
when the supply drops below V
CCMIN.
Power Save Mode
Procedure To Put The LM1253A Into Power Save Mode
or Power Off Blanking
If the monitor has a power save mode the following proce-
dure should be used to put the LM1253A into power save
mode. This should be used for both power save modes
initiated from the video card and power save modes initiated
by a user on the front panel of the monitor.
1.
Set Bias and Brightness registers (8434h – 8437h) to 0.
2.
Set the LM1253A to blank video by setting register
8439h to 01h.
3.
Turn off the 8V and 80V supply to the LM2453.
4.
Set the LM1253A to power save by setting register
8439h to 02h.
LM1253A
www.national.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LM1253AN | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator |
| LM-1256 | 制造商:ROHM 制造商全称:Rohm 功能描述:16 x 16 matrix displays |
| LM-1256_1 | 制造商:ROHM 制造商全称:Rohm 功能描述:16】16 matrix displays |
| LM-1256LB1 | 制造商:ROHM 制造商全称:Rohm 功能描述:16】16 matrix displays |
| LM125AN | 制造商:NSC 制造商全称:National Semiconductor 功能描述:VOLTAGE REGULATORS |
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