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参数资料
| 型号： | LM1253AAE/NA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 画面叠加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDIP28 |
| 封装： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件页数： | 20/61页 |
| 文件大小： | 1671K |
| 代理商： | LM1253AAE/NA |
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Micro-Controller Interface
The micro-controller interfaces to the LM1253A pre-amp via
an I
2C interface. The protocol of the interface begins with a
Start Pulse followed by a byte comprised of a seven bit Slave
Device Address and a Read/Write bit. Since the first byte is
composed of both the address and the read/write bit the
address of the LM1253A for writing is BAh (1011 1010) and
the address for reading is BBh (1011 1011). The develop-
ment software provided by National Semiconductor will au-
tomatically take care of the difference between the read and
write addresses if the target address under the communica-
tions tab is set to BAh.
Figures 39, 40 show a write and read
sequence across the I
2C interface.
Write Sequence
The write sequence begins with a start condition which
consists of the master pulling SDA low while SCL is held
high. The slave device address is next sent. The address
byte is made up of an address of seven bits (7-1) and the
read/write bit (0). Bit 0 is low to indicate a write operation.
Each byte that is sent is followed by an acknowledge. When
SCL is high the master will release the SDA line. The slave
must pull SDA low to acknowledge. The register to be written
to is next sent in two bytes, the least significant byte being
sent first. The master can then send the data, which consists
of one or more bytes. Each data byte is followed by an
acknowledge bit. If more than one data byte is sent the data
will increment to the next address location. See
Figure 39.
Read Sequence
Read sequences are comprised of two I
2C transfer se-
quences: The first is a write sequence that only transfers the
two byte address to be accessed. The second is a read
sequence that starts at the address transferred in the previ-
ous address only write access and increments to the next
address upon every data byte read. This is shown in
Figure
40.
DS101265-45
FIGURE 39. I
2C Write Sequence
LM1253A
www.national.com
27
相关PDF资料 |
PDF描述 |
|---|---|
| LM1267NA/NOPB | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| LM1269NA/NOPB | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| LM1276AAA/NA | 1 CHANNEL, VIDEO PREAMPLIFIER, PDIP28 |
| LM1279AN/NOPB | 3 CHANNEL, VIDEO AMPLIFIER, PDIP20 |
| LM1279N/NOPB | 1 CHANNEL, VIDEO AMPLIFIER, PDIP20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LM1253AN | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator |
| LM-1256 | 制造商:ROHM 制造商全称:Rohm 功能描述:16 x 16 matrix displays |
| LM-1256_1 | 制造商:ROHM 制造商全称:Rohm 功能描述:16】16 matrix displays |
| LM-1256LB1 | 制造商:ROHM 制造商全称:Rohm 功能描述:16】16 matrix displays |
| LM125AN | 制造商:NSC 制造商全称:National Semiconductor 功能描述:VOLTAGE REGULATORS |
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