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参数资料
| 型号： | LM1253AAE/NA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 画面叠加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDIP28 |
| 封装： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件页数： | 40/61页 |
| 文件大小： | 1671K |
| 代理商： | LM1253AAE/NA |
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Control Register Definitions (Continued)
Red Bias Clamp Pulse Amplitude Control Register (I
2C address 8436h).
REGISTER NAME: RBIASCTRL (8436h)
Bit 7
Bit 0
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
Bits 7–0: Red Channel Bias Clamp Pulse Amplitude Control. These six bits determine the bias clamp value for its pulse
amplitude.
Brightness Amplitude Control Register (I
2C address 8437h).
REGISTER NAME: BRIGHTCTRL (8437h)
Bit 7
Bit 0
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
Bits 7–0: Brightness Amplitude Control. These six bits determine amplitude of brightness for all three channels.
DC Offset and OSD Contrast Control Register (I
2C address 8438h).
REGISTER NAME: DCOFFSET (8438h)
Bit 7
Bit 0
BP2
BP1
BP0
OSD C1
OSD C0
DC2
DC1
DC0
Bits 2–0: DC Offset Control. These three bits determine the active video DC offset to all three channels.
Bits 4–3: OSD Contrast. These two bits determine the OSD contrast.
Bits 7–5: Blanking pedestal. These three bits determine the blanking pedestal offset for all three channels.
Global Video Control Register (I
2C address 8439h).
REGISTER NAME: GLOBALCTRL (8439h)
Bit 7
Bit 0
RSV
PS
BV
Bit 0:
Blank Video. When this bit is a one, the video output is blanked. When this bit is a zero normal video is output.
Bit 1:
Power Save. When this bit is a one, the analog circuits are shutdown to support sleep mode. When this bit is a zero
the analog circuits are enabled for normal operation. See the Power Save Mode section.
Bits 7–2: RESERVED.
PLL Frequency Range Control Register (I
2C address 843Eh).
REGISTER NAME: PLLFREQRNG (843Eh)
Bit 7
Bit 0
RSV
IVS1
IVS0
PFR1
PFR0
Bits 1–0: PLL Frequency Range Control. These bits assist the PLL in locking to the desired pixel frequency. PLL Range should
be set as shown in
Table 12.
Bits 3–2: Sets the approximate Free Run Frequency.
00: 38 kHz, 01: 43 kHz, 10: 47 kHz, 11: 52 kHz.
Bits 7–4: RESERVED. Set to 0
LM1253A
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LM1253AN | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator |
| LM-1256 | 制造商:ROHM 制造商全称:Rohm 功能描述:16 x 16 matrix displays |
| LM-1256_1 | 制造商:ROHM 制造商全称:Rohm 功能描述:16】16 matrix displays |
| LM-1256LB1 | 制造商:ROHM 制造商全称:Rohm 功能描述:16】16 matrix displays |
| LM125AN | 制造商:NSC 制造商全称:National Semiconductor 功能描述:VOLTAGE REGULATORS |
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