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参数资料
| 型号： | LM12L458CIVX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 14/29页 |
| 文件大小： | 891K |
| 代理商： | LM12L458CIVX |
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Bits 12–15 are used to store the user-programmable acqui-
sition time. The Sequencer keeps the internal S/H in the
acquisition mode for a fixed number of clock cycles (nine
clock cycles, for 12-bit + sign conversions and two clock
cycles for 8-bit + sign conversions or “watchdog” compari-
sons) plus a variable number of clock cycles equal to twice
the value stored in Bits 12–15. Thus, the S/H’s acquisition
time is (9 + 2D) clock cycles for 12-bit + sign conversions
and (2 + 2D) clock cycles for 8-bit + sign conversions or
“watchdog” comparisons, where D is the value stored in Bits
12–15. The minimum acquisition time compensates for the
typical internal multiplexer series resistance of 2 k
, and any
additional delay created by Bits 12–15 compensates for
source resistances greater than 80
. (For this acquisition
time discussion, numbers in ( ) are shown for the LM12L458
operating at 6 MHz.) The necessary acquisition time is de-
termined by the source impedance at the multiplexer input. If
the source resistance (R
S) < 80
and the clock frequency is
6 MHz, the value stored in bits 12–15 (D) can be 0000. If R
S
> 80
, the following equations determine the value that
should be stored in bits 12–15.
D=0.45xR
S xfCLK
for 12-bits + sign
D=0.36xR
S xfCLK
for 8-bits + sign and “watchdog”
A4 A3 A2 A1 A0
Purpose
Type
D7
D6
D5
D4
D3
D2
D1
D0
000
Instruction RAM
(RAM Pointer = 00)
R/W
V
IN
V
IN+
Pause
Loop
0to
0
111
000
R/W
Acquisition Time
Watch-
dog
8/12
Timer
Sync
0to
1
111
000
Instruction RAM
(RAM Pointer = 01)
R/W
Comparison Limit #1
0to
0
111
000
R/W
Don’t Care
>/<
Sign
0to
1
111
000
Instruction RAM
(RAM Pointer = 10)
R/W
Comparison Limit #2
0to
0
111
000
R/W
Don’t Care
>/<
Sign
0to
1
111
1
0000
Configuration
Register
R/W
I/O Sel
Auto
Zero
ec
Chan
Mask
Stand-
by
Full Cal
Auto-
Zero
Reset
Start
1
0001
R/W
Don’t Care
DIAG
Test
=0
RAM Pointer
1
0010
Interrupt Enable
Register
R/W
INT7
Don’t
Care
INT5
INT4
INT3
INT2
INT1
INT0
1
0011
R/W
Number of Conversions in Conversion FIFO to
Generate INT2
Sequencer Address to
Generate INT1
1
0100
Interrupt Status
Register
R
INST7
“0”
INST5
INST4
INST3
INST2
INST1
INST0
1
0101
R
Actual Number of Conversions Results in
Conversion FIFO
Address of Sequencer
Instruction being
Executed
1
0110
Timer
Register
R/W
Timer Preset: Low Byte
1
0111
R/W
Timer Preset: High Byte
1
1000
Conversion
FIFO
R
Conversion Data: LSBs
1
1001
R
Address or Sign
Sign
Conversion Data: MSBs
1
1010
Limit Status
Register
R
Limit #1 Status
1
1011
R
Limit #2 Status
FIGURE 14. LM12L458 Memory Map for 8-Bit Wide Data Bus (BW = “1” and Test Bit = “0”)
LM12L458
www.national.com
21
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