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参数资料
| 型号： | LM12L458CIVX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 27/29页 |
| 文件大小： | 891K |
| 代理商： | LM12L458CIVX |
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Electrical Characteristics (Continued)
01171104
Note 7: VA+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V
+ pin to assure
conversion/comparison accuracy.
Note 8: Accuracy is guaranteed when operating at fCLK = 6 MHz.
Note 9: With the test condition for VREF =VREF+ VREF given as +2.5V, the 12-bit LSB is 305 V and the 8-bit/“Watchdog” LSB is 4.88 mV.
Note 10: Typical figures are at TA = 25C and represent most likely parametric norm.
Note 11: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See Figures 7, 8).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between 1 to 0 and 0 to +1 (see Figure 9).
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to +2.5V. The measured value is referred to the resulting
output value when the inputs are driven with a 1.25V signal.
Note 15: Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with VA+ and VD+ at the specified extremes.
Note 16: VREFCM (Reference Voltage Common Mode Range) is defined as (VREF+ +VREF)/2.
Note 17: The LM12L458’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in
a repeatability uncertainty of ±0.10 LSB.
Note 18: The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44
clock cycles) are used (see Figure 15). One additional clock cycle is used to read the conversion result stored in the FIFO, for a total of 56 clock cycles per
conversion. The Throughput Rate is fCLK (MHz)/N, where N is the number of clock cycles/conversion.
Test Circuits and Waveforms
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FIGURE 1. TRI-STATE Test Circuits and Waveforms
LM12L458
www.national.com
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