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参数资料
| 型号： | LM12L458CIVX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 9/29页 |
| 文件大小： | 891K |
| 代理商： | LM12L458CIVX |
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Pin Descriptions
V
A+, VD+ Analog
and digital supply voltage pins. The
LM12L458’s supply voltage operating range is
+3.0V to +5.5V. Accuracy is guaranteed only if
V
A+ and VD+ are connected to the same power
supply. Each pin should have a parallel combina-
tion of 10 F (electrolytic or tantalum) and 0.1 F
(ceramic) bypass capacitors connected between
it and ground.
D0–D15
The internal data input/output TRI-STATE buffers
are connected to these pins. These buffers are
designed to drive capacitive loads of 100 pF or
less. External buffers are necessary for driving
higher load capacitances. These pins allows the
user a means of instruction input and data output.
With a logic high applied to the BW pin, data lines
D8–D15 are placed in a high impedance state
and data lines D0–D7 are used for instruction
input and data output when the LM12L458 is
connected to an 8-bit wide data bus. A logic low
on the BW pin allows the LM12L458 to exchange
information over a 16-bit wide data bus.
RD
Input for the active low READ bus control signal.
The data input/output TRI-STATE buffers, as se-
lected by the logic signal applied to the BW pin,
are enabled when RD and CS are both low. This
allows the LM12L458 to transmit information onto
the data bus.
WR
Input for the active low WRITE bus control signal.
The data input/output TRI-STATE buffers, as se-
lected by the logic signal applied to the BW pin,
are enabled when WR and CS are both low. This
allows the LM12L458 to receive information from
the data bus.
CS
Input for the active low Chip Select control signal.
A logic low should be applied to this pin only
during a READ or WRITE access to the
LM12L458. The internal clocking is halted and
conversion stops while Chip Select is low. Con-
version resumes when the Chip Select input sig-
nal returns high.
ALE
Address Latch Enable input. It is used in systems
containing a multiplexed data bus. When ALE is
asserted high, the LM12L458 accepts informa-
tion on the data bus as a valid address. A high-
to-low transition will latch the address data on
A0–A4 and the logic state on the CS input. Any
changes on A0–A4 and CS while ALE is low will
not affect the LM12L458. See Figure 10. When a
non-multiplexed bus is used, ALE is continuously
asserted high. See Figure 11.
CLK
External clock input pin. The LM12L458 operates
with an input clock frequency in the range of
0.05 MHz to 8 MHz.
A0–A4
The LM12L458’s address lines. They are used to
access all internal registers, Conversion FIFO,
and Instruction RAM.
SYNC
Synchronization input/output. When used as an
output, it is designed to drive capacitive loads of
100 pF or less. External buffers are necessary for
driving higher load capacitances. SYNC is an
input if the Configuration register’s “I/O Select” bit
is low. A rising edge on this pin causes the inter-
nal S/H to hold the input signal. The next rising
clock edge either starts a conversion or makes a
comparison to a programmable limit depending
on which function is requested by a programming
instruction. This pin will be an output if “I/O Se-
lect” is set high. The SYNC output goes high
when a conversion or a comparison is started and
low when completed. (See Section 2.2). An inter-
nal reset after power is first applied to the
LM12L458 automatically sets this pin as an input.
BW
Bus Width input pin. This input allows the
LM12L458 to interface directly with either an 8- or
16-bit data bus. A logic high sets the width to 8
bits and places D8–D15 in a high impedance
state. A logic low sets the width to 16 bits.
INT
Active low interrupt output. This output is de-
signed to drive capacitive loads of 100 pF or less.
External buffers are necessary for driving higher
load capacitances. An interrupt signal is gener-
ated any time a non-masked interrupt condition
takes place. There are eight different conditions
that can cause an interrupt. Any interrupt is reset
by reading the Interrupt Status register. (See Sec-
tion 2.3.)
DMARQ
Active high Direct Memory Access Request out-
put. This output is designed to drive capacitive
loads of 100 pF or less. External buffers are
necessary for driving higher load capacitances. It
goes high whenever the number of conversion
results in the conversion FIFO equals a program-
mable value stored in the Interrupt Enable regis-
ter. It returns to a logic low when the FIFO is
empty.
GND
Ground connection. It should be connected to a
low resistance and inductance analog ground re-
turn that connects directly to the system power
supply ground.
IN0–IN7
These are the eight analog inputs. A given chan-
nel is selected through the instruction RAM. Any
of the channels can be configured as an indepen-
dent single-ended input. Any pair of channels,
whether adjacent or non-adjacent, can operate as
a fully differential pair.
V
REF
This
is
the
negative
reference
input.
The
LM12L458 operates with 0V
≤ V
REF
≤ V
REF+.
This pin should be bypassed to ground with a
parallel combination of 10 F and 0.1 F (ce-
ramic) capacitors.
V
REF+
Positive reference input. The LM12L458 operate
with 0V
≤ V
REF+
≤ V
A+. This pin should be by-
passed to ground with a parallel combination of
10 F and 0.1 F (ceramic) capacitors.
N.C.
This is a no connect pin.
LM12L458
www.national.com
17
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