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参数资料
| 型号： | LM12L458CIVX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 24/29页 |
| 文件大小： | 891K |
| 代理商： | LM12L458CIVX |
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Converter Characteristics (Continued)
The following specifications apply for V
A+=VD+ = +3.3V, VREF+ = +2.5V, VREF = 0V, 12-bit + sign conversion mode, fCLK =
6.0 MHz, R
S =25
, source impedance for V
REF+ and VREF
≤ 25, fully-differential input with fixed 1.25V common-mode volt-
age, and minimum acquisition time unless otherwise specified. Boldface limits apply for T
A =TJ =TMIN to TMAX; all other
limits T
Symbol
Parameter
Conditions
Typical
Limits
Units
8-Bit + Sign and “Watchdog” Mode DC
Common Mode Error
±1/8
LSB
Multiplexer Channel-to-Channel
Matching
±0.05
LSB
V
IN+
Non-Inverting Input Range
GND
V (min)
V
A+
V (max)
V
IN
Inverting Input Range
GND
V (min)
V
A+
V (max)
V
IN+ VIN
Differential Input Voltage Range
V
A
+
V (min)
V
A+
V (max)
Common Mode Input Voltage Range
GND
V (min)
V
A+
V (max)
PSS
Power Supply
Sensitivity
Zero Error
V
A+=VD+ = +3.3V ±10%
±0.2
±1.75
LSB (max)
Full-Scale Error
V
REF+ = 2.5V, VREF = GND
±0.4
±2
LSB (max)
Linearity Error
±0.2
LSB
C
REF
V
REF+/VREF Input Capacitance
85
pF
C
IN
Selected Multiplexer Channel Input
Capacitance
75
pF
Converter AC Characteristics
The following specifications apply for V
A+=VD+ = +3.3V, VREF+ = +2.5V, VREF = 0V, 12-bit + sign conversion mode, fCLK =
6.0 MHz, R
S =25
, source impedance for V
REF+ and VREF
≤ 25, fully-differential input with fixed +1.25V common-mode
voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T
A =TJ =TMIN to TMAX; all other
limits T
Symbol
Parameter
Conditions
Typical
Limits
Units
Clock Duty Cycle
50
40
% (min)
60
% (max)
t
C
Conversion Time
13-Bit Resolution, Sequencer
State S5 (Figure 15)
44 (t
CLK)
44 (t
CLK)+50ns
(max)
9-Bit Resolution, Sequencer State
S5 (Figure 15)
21 (t
CLK)
21 (t
CLK)+50ns
(max)
t
A
Acquisition Time
Sequencer State S7 (Figure 15)
Built-in minimum for 13-Bits
9(t
CLK)
9(t
CLK)+50ns
(max)
Built-in minimum for 9-Bits and
“Watchdog” mode
2(t
CLK)
2(t
CLK)+50ns
(max)
t
Z
Auto-Zero Time
Sequencer State S2 (Figure 15)76 (t
CLK)
76 (t
CLK)+50ns
(max)
t
CAL
Full Calibration Time
Sequencer State S2 (Figure 15)
4944 (t
CLK)
4944 (t
CLK)+50ns
(max)
Throughput Rate (Note 18)
107
106
kHz (min)
t
WD
“Watchdog” Mode Comparison
Time
Sequencer States S6, S4, and S5
11 (t
CLK)
11 (t
CLK)+50ns
(max)
t
PU
Power-Up Time
10
ms
t
WU
Wake-Up Time
10
ms
LM12L458
www.national.com
4
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