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参数资料
| 型号： | LM12L458CIVX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 26/29页 |
| 文件大小： | 891K |
| 代理商： | LM12L458CIVX |
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Digital Timing Characteristics
The following specifications apply for V
A+=VD+ = +3.3V, tr =tf = 3 ns, and CL = 100 pF on data I/O, INT and DMARQ lines
unless otherwise specified. Boldface limits apply for T
Symbol (See
Parameter
Conditions
Typical
Limits
Units
1, 3
CS or Address Valid to ALE Low Set-Up
Time
40
ns (min)
2, 4
CS or Address Valid to ALE Low Hold
Time
20
ns (min)
5
ALE Pulse Width
45
ns (min)
6
RD High to Next ALE High
35
ns (min)
7
ALE Low to RD Low
20
ns (min)
8
RD Pulse Width
100
ns (min)
9
RD High to Next RD or WR Low
100
ns (min)
10
ALE Low to WR Low
20
ns (min)
11
WR Pulse Width
60
ns (min)
12
WR High to Next ALE High
75
ns (min)
13
WR High to Next RD or WR Low
140
ns (min)
14
Data Valid to WR High Set-Up Time
40
ns (min)
15
Data Valid to WR High Hold Time
30
ns (min)
16
RD Low to Data Bus Out of TRI-STATE
30
10
ns (min)
70
ns (max)
17
RD High to TRI-STATE
R
L =1k
30
10
ns (min)
110
ns (max)
18
RD Low to Data Valid (Access Time)
30
10
ns (min)
95
ns (max)
20
Address Valid or CS Low to RD Low
20
ns (min)
21
Address Valid or CS Low to WR Low
20
ns (min)
19
Address Invalid from RD or WR High
10
ns (min)
22
INT High from RD Low
30
10
ns (min)
60
ns (max)
23
DMARQ Low from RD Low
30
10
ns (min)
60
ns (max)
Electrical Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > (VA+orVD+)), the current at that pin should be limited to 5 mA.
The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of 5 mA, to simultaneously exceed the power supply
voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction
to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax =(TJmax TA)/θJA or the
number given in the Absolute Maximum Ratings, whichever is lower.
Note 5: Human body model, 100 pF discharged through a 1.5 k
resistor.
Note 6: Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND
will not damage the LM12L458. However, errors in the A/D conversion can occur if these diodes are forward biased by more than 100 mV. As an example, if VA+
is 3.0 VDC, full-scale input voltage must be ≤3.1 VDC to ensure accurate conversions.
LM12L458
www.national.com
6
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