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参数资料
| 型号： | LM27262MTDX/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO48 |
| 封装： | TSSOP-48 |
| 文件页数： | 22/22页 |
| 文件大小： | 1105K |
| 代理商： | LM27262MTDX/NOPB |
Electrical Characteristics (Note 5),(Note 6) V
CC5V = 5V unless otherwise specified. (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRON De-assertion
Delay
Delay of VRON falling edge by the internal logic
50
nsec
REFINT
REFINT Leakage
Current
REFINT = 3.3V or GND
±2
A
Logic Low Input
Voltage
0.5
V
Logic High Input
Voltage
3.0
V
PHASES
PHASES Leakage
Current
V
PHASES =0V
- 25
A
V
PHASES = 3.3V
4
A
PHASES Open Circuit
Voltage
10M
to Ground
2.8
V
Logic Low Max Input
Voltage
0.2
V
Logic High Min Input
Voltage
Relative to Vcc (5V nominal)
-0.2
V
LOGIC OUTPUTS: DRIVEx
Output High Voltage
Output Source Current is 10 mA
3.5
V
Output Source Current is 0 mA (no load)
4.5
Output Low Voltage
Output Sink Current is 10 mA
0.3
V
Low-to-High Transition
Time
10% to 90% of V
CC5V,
C
LOAD = 50pF
20
ns
High-to-Low Transition
Time
90% to 10% of V
CC5V,
C
LOAD = 50pF
20
ns
VIDPGD
VIDPGD Output Max
Low Voltage
VIDPGD sinking 4mA (open drain)
0.17
0.25
V
VIDPGD Leakage
Current
VIDPGD = 5.5V
1
10
A
VIDPGD Assertion
Delay
VRON assertion to VIDPGD assertion
(SOFTCAP = 0.01F)
2
ms
VIDPGD De-assertion
Delay
VRON de-assertion to VIDPGD de-assertion
50
ns
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics table.
Note 2: The maximum allowable power dissipation is calculated by using PDmax =(TJMAX -TA)/θJA , where TJMAX is the maximum junction temperature, TA is the
ambient temperature, and
θJA is the junction-to-ambient thermal resistance of the specified package. The 1.56W rating results from using 150C, 25C, and 80C/W
for TJMAX,TA, and θJA respectively. The θJA of 90C/W represents the worst-case condition with no heat sinking of the 48-Pin TSSOP. Heat sinking allows the safe
dissipation of more power. The Absolute Maximum power dissipation should be de-rated by 12.5mW per C above 25C ambient. The LM27262 actively limits its
junction temperature to about 165C.
Note 3: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook available from National Semiconductor Corporation.
Note 4: For testing purposes, ESD was applied using the human-body model, a 100pF capacitor discharged through a 1.5k
resistor.
Note 5: All limits are guaranteed at room temperature (standard face type) and at temperature extremes (bold face type). All room temperature limits are 100%
production tested. All limits at temperature extremes are guaranteed via correlation using Statistical Quality Control (SQC) methods. All limits are used to calculate
Average Outgoing Quality Level (AOQL).
Note 6: A “typical” specification is the center of characterization data distribution taken with TA =TJ = 25C. Typical data are not guaranteed.
LM27262
www.national.com
9
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