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参数资料
| 型号： | LM27262MTDX/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO48 |
| 封装： | TSSOP-48 |
| 文件页数： | 8/22页 |
| 文件大小： | 1105K |
| 代理商： | LM27262MTDX/NOPB |
Operation Descriptions (Continued)
T
SOFTSTART-RAMP =(VCORE/ISOFTCAP)CSOFTCAP;
T
VIDPGD =TSOFTSTART-RAMP x 0.5V/VCORE;
T
TURN-ON =TVIDPGD +(VCORE/ISOFTCAP)CSOFTCAP; where
I
SOFTCAP = 3.2A and Volt, Amp and Farad units are used.
For example:
If T
SOFTSTART-RAMP
) 5 msec for V
CORE = 1.55V and Css =
10nF then T
VIDPGD
) 1.6 msec and T
TURN-ON = 6.6 msec. If
T
SOFTSTART-RAMP
) 3.6 msec for V
CORE = 1.15V and Css =
10nF then T
VIDPGD
) 1.6 msec and T
TURN-ON = 5.2 msec
SOFT STOP
The soft-stop feature forces a well-controlled power off tran-
sition. The output voltage ramps down smoothly, eliminating
the possibility of a large negative voltage at the output. This
feature eliminates the large need for a Schottky protection
diode or a clamp transistor at the load.
The LM27262 has an internal 50k
resistor connected to the
SOFTCAP pin that discharges the SOFTCAP capacitor. The
soft-stop ramp-down time is approx. 9msec with a 33nF
capacitor, or approximately 5 x RC, where R is 50k
, and C
is the soft-start capacitor.
VID-CODE CONTROLLED V
CORE TRANSITIONS
The VID transition slew rate is set by an external resistor
connected between the VIDSLEW and SOFTCAP pins. This
permits an additional level of slew rate control beyond that
provided by the soft-start function.
UVP, OVP and OCP SHUTDOWN PROGRAMMABLE
Delay
If PWRGD is de-asserted for any reason, the voltage regu-
lator can disable its output and latch itself off. Different
systems can tolerate various fault conditions for different
time durations. A programmable delay feature enables the
system designer to chose how long the supply will wait
following the detection of an OVP or UVP event prior to
shutting down. By adding a capacitor to the DELAY pin, pin
34, the latching of fault events can be delayed. If the DELAY
pin is grounded, latch off is defeated entirely. The following
formula should be used for calculating a programming ca-
pacitor value:
CDELAY = TDELAY x 12.5A/1.4V or
TDELAY/112k
where C is in Farads, 1.4V is the
“DELAY Threshold Voltage”, and 12.5A is the
“DELAY Charge Current”. For example,
CDELAY = 0.22F programs a 25ms delay.
Grounding the DELAY pin will disable the latch off function.
This can be most helpful during system de-bug or if the
latch-off feature is not desired for some reason.
2-, 3- or 4-PHASE OPERATION
2-, 3- or 4-phase operation is user selectable. For lower
current designs it may be desirable to use fewer than 4
phases.
LOGIC INPUTS and OUTPUTS - GENERAL
All logic control inputs have hysteresis that increases noise
immunity and, particularly for the VRON signal, enables a
designer to turn the LM27262 on from a 3.3V rail via an
external RC-delay circuit. Note that the logic outputs are not
short circuit protected and must not be short-circuited to
either power rails or ground.
LOOP COMPENSATION
An RC network connected between the VFB and VCOMP
pins compensates the feedback loop’s gain/phase charac-
teristics. These two pins are respectively, the input and
output of the error amplifier. Feedback loops such as these
are best compensated through the use of an empirical ap-
proach. The best approach is to measure the control to
output transfer function and then design an appropriate error
amplifier compensation.
Component Selection
POWER PATH COMPONENT SELECTION
The choice of power path components is critical to achieving
a properly behaved regulator. Design considerations usually
include such things as efficiency, transient response, output
ripple, size and cost. The process tends to be somewhat
iterative while converging on a workable design.
The first decision that must be made is the number of phases
to use. The maximum load current that the design must
deliver usually dictates this. With the power devices avail-
able at the time of this writing, the practical upper limit is
about 20 to 25 amps per phase. Trying to run higher per
phase load currents results in thermal problems as well as
the inability to maintain an all surface-mount design. In some
instances, it is possible to pull higher phase currents if the
peak’s duration is relatively short and the average current is
well below peak. Another possible criteria for selecting the
number of phases is to capitalize on the ripple current can-
cellation effects of multiphase designs. In theory, at a V
IN to
V
OUT ratio equal to the number of phases, the input and
output ripple currents approach zero. If the design will run
close to this “sweet spot” it may influence the number of
phases selected. For instance, adding a phase may prove
most advantageous.
One’s initial reaction to increased phase count is that the
solution becomes much more costly. But this assumption
isn’t always correct. In theory, the total energy stored in the
output inductors decreases as phases are added. This is
due in part to the ripple cancellation effects and in part to the
energy storage being a function of the square of the inductor
currents. So for equal inductor values in a two-phase design,
the energy stored is only 50% that of a single phase design.
In practice, for equal output ripple, the inductance in each
phase of a 2-phase design could be about 12 that of a
comparable single phase design. Therefore, energy storage
per inductor is only 25% that of a one phase design. So,
although there may be two inductors in the 2-phase design,
they are each much smaller, lighter and hopefully lower cost,
than the comparable single-phase solution. As for MOSFET
selection, since the total current being switched is the same
regardless the number of phases, in theory, the total Rds(on)
required is the same as well. It just gets split into more
packages in the multi-phase design. Some difficult to char-
acterize advantages of a higher phase count relate to MOS-
FET parasitics. For instance, the body diode reverse recov-
ery effects of the low side switch adversely effect the
switching loses in a buck regulator. Larger FETs for both the
low side and high side switches will have much greater
losses than smaller devices switching lower currents. Spuri-
ous turn-on of the low side FET due to its Miller capacitance
is also less problematic in smaller devices. The result is that
in many cases, the higher phase count design will prove to
be somewhat more efficient than a lower phase count design
that can provide comparable full load current.
LM27262
www.national.com
16
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