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参数资料
| 型号： | LM27262MTDX/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO48 |
| 封装： | TSSOP-48 |
| 文件页数： | 9/22页 |
| 文件大小： | 1105K |
| 代理商： | LM27262MTDX/NOPB |
Component Selection (Continued)
Since VRD-10 designs must support large load transients
while maintaining very tight output regulation, a good place
to start the design is the output capacitors.
OUTPUT CAPACITOR SELECTION
For designs that will be subjected to large load current
transients, the output capacitor array is probably the best
place to start. It is assumed that the full amplitude of the load
current step will be drawn from the output capacitors for a
short time. As such, there will be a significant droop in the
output voltage that’s a function of the step size and the
output capacitor’s impedance. The output voltage step will
have three basic components. The first is a more or less
vertical edge equal to the ESR (Equivalent Series Resis-
tance) of the output caps multiplied by the load step ampli-
tude or
I x ESR. There’s also a component equal to the ESL
(Equivalent Series Inductance) multiplied by the rate of
change of the load current, (
I/t) x ESL. The ESL induced
spike is usually small in value and short lived, assuming a
clean board layout with good high frequency decoupling, and
can usually be ignored. In sizing the output capacitors, a
good starting point is to assume that the ESR step will be
20% to 50% of the allotted transient voltage spec. The low
end of the range will apply to ceramic capacitors and the
high end of the range to tantalum or aluminum electrolytic
devices. The remainder of the tolerance can be allocated to
the output capacitor’s droop voltage. The droop rate,
V/t,
is equal to I
STEP/COUT, where Istep is the amplitude of the
load transient. The total droop amplitude is equal to
V/t
multiplied by the time it takes for the regulator to get the
output voltage slewing in the opposite direction. See Figure
5 for details.
In a design with voltage positioning, the ideal ESR of the
output capacitor array should be less than or equal to the
load line slope. So for a VRD-10 design we should assume
1.5m
for the output capacitor ESR.
In a four-phase design, it’s likely that the latency prior to
getting a high-side switch turned on is approximately 1/4 of a
full cycle. An estimate of about twice that, or around 1.5s, is
a good place to start for making the droop calculation. As an
example, assume a 50 amp load step and a tolerance of
85mV with high performance polymer capacitors: Using a
390F, 5m
capacitor, the design requires a minimum of 4 in
parallel to meet the ESR estimate. The droop in 1.5s would
be:
Droop = 1.5s x 50A/1560F = 48mV
Add this to the 75mV ESR droop and we can see the spec is
not met. Therefore several additional capacitors must be
added. Rerunning the numbers with 6 capacitors we get:
Droop = 1.5s x 50A/2340F = 32mV
Plus an ESR step of 50A x 0.833m
+ 32mV = 73.6mV
In general, it will be necessary to add high frequency decou-
pling as well as the bulk capacitance calculated above. An
array of at least 20, 22F, 1206 case ceramics is recom-
mended. They should be as close to the CPU as possible.
With the output capacitors chosen, an upper bound can be
established for the inductor value:
L < C
OUT x(VIN (MIN) -VOUT(MAX)) x ESR /
I
OUT
This value inductor should be installed in each phase. Larger
inductor values will result in a delay in the output voltage
recovery to a load step. Smaller values will store less energy
(lower cost) but will increase the output ripple. Since the
peak switch currents will also be higher, the efficiency is
likely to suffer somewhat with smaller inductors.
Assuming a minimum input voltage of 12V and 1.5V out with
a 50A load step and the capacitors selected above,
L < 2340F x (12V- 1.5V) x 0.833 m
/50A
L < 0.41 H
Something around 0.5H will be the closest standard value
and should prove adequate. Since this value is slightly
greater than desired, dynamic performance will suffer
slightly.
If this value will yield excessive ripple current at maximum
input voltage (greater than about 40% of the single phase
DC current), then a larger inductor should be considered and
therefore, optimal dynamic performance will not be obtained.
The tradeoff is typically efficiency vs. dynamic performance.
During a load-off transition, the extra energy stored in the
inductors will end up in the output capacitors. This magnetic
energy, LI
2/2, will be stored in the output capacitors as
CV
2/2. The energy already in the output capacitor prior to the
transient, and that left in the inductor after the event, must
also be accounted for.
Therefore:
V
MAX = [(n x L/C) x ((IMAX/n)
2–(I
MIN/n)
2)+V
init
2]1/2
Where V
MAX is the peak output voltage, n is the number of
phases, I
MAX is the high load current , IMIN is the low load
current, C is the output capacitance, L is the per phase
inductor value, and V
init is the output voltage prior to the load
dump.
From our example assuming a 70A max load and a 50A step:
V
MAX = (4 x 0.50H x ((70A / 4)
2 – 20/4)2) / 2340F +
1.4452)
1/2
20083425
FIGURE 5. Output Transient Response
20083426
FIGURE 6. Normalized Pk-Pk Output Ripple As A
Function Of Duty Factor and Number Of Phases
LM27262
www.national.com
17
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