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参数资料
| 型号： | LM27262MTDX/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO48 |
| 封装： | TSSOP-48 |
| 文件页数： | 6/22页 |
| 文件大小： | 1105K |
| 代理商： | LM27262MTDX/NOPB |
Operation Descriptions
GENERAL
The LM27262 is a selectable 2-, 3-, or 4-phase step down
switching regulator controller. It’s a fixed-frequency, voltage-
mode control PWM with user programmable average current
modulation of the reference voltage. This approach imparts a
pseudo current mode behavior to the control loop as well as
load line shaping for improved dynamic performance. The
individual phase currents are continuously monitored and
the duty cycles of each phase are adjusted as necessary so
that the phase currents are all kept equal. The MOSFET
drivers are contained in separate driver chips. This offers
several advantages. From a cost standpoint, the largest
amount of die area in most controllers is used for the drivers.
As such, with external drivers, only the required drivers for a
given design need be purchased. From an electrical stand-
point, the drivers produce large pulse currents that tend to
disturb the analog circuitry close by, particularly within the
controller. By moving the drivers off chip, these pulse cur-
rents can be localized to the drivers themselves. PCB layout
is also simplified since the drivers will not need long, hi di/dt
traces. The drivers can be located very close to their respec-
tive MOSFETs. This is especially advantageous in a mul-
ti–phase design that, by it’s nature, occupies a fair amount of
board real estate. Shorter gate drive runs will also help
minimize radiated emissions from the power supply. The
result is much better-behaved control circuitry and less like-
lihood of needing several PCB iterations to optimize the
circuit’s performance.
CURRENT BALANCING CIRCUIT
In order to ensure current balance between phases, the
LM27262 measures the instantaneous load current for the
“on” phase and forces this current to be equal to the average
of all the active phase currents.
Refer to Figure 3. Only two phases are shown for simplicity.
The circuitry in Figure 3 is duplicated on the other two
phases of a 4-phase design. The VIL pins connect to the
output side of the current sense resistors, while the VIH pins
connect to the inductor side of the sense resistors. All of the
VIL signals are summed through the internal 10k
resistors
so that the difference between the signals VILAVG and
VIHAVG represents the average value of all the correspond-
ing sense voltages.
Amplifier A1 converts the difference, VIHAVG-VILAVG, to a
ground-referenced signal, which represents the instanta-
neous average current per phase. Amplifier A2 converts the
instantaneous current information for phase A from a differ-
ential to a ground referenced signal. Amplifier A4 acts as an
error amplifier, the output of which drives an adjustable
current source, I2. Current source I1 provides a continuous
current for charging the internal ramp capacitor, C
RAMP,
while I2 makes slight adjustments to this charging current.
The resulting ramp voltage is ultimately compared to the
voltage loop’s error amplifier output to control the regulator’s
pulse width. When the PWM comparator trips, it also turns
on the ramp generator’s reset transistor and dumps the ramp
capacitor. Amplifiers A3 and A5 perform the same function
for Phase C by controlling an identical ramp generator. In
summary, the slope of the PWM generator’s ramp signal is
adjusted as required to keep the phase currents balanced.
For instance, if the phase A current is a bit too high com-
pared to the average phase current, the slope of the PWM
ramp for this phase is increased slightly. This tends to turn
the phase off a bit early and reduce its output current.
UNDER VOLTAGE LOCK OUT (UVLO)
The 5V supply input has a UVLO function with hysteresis,
assuring stable, predictable start-up performance.
POWER GOOD FUNCTION
The PWRGD window is -12% to +230mV (typical) of the
programmed output voltage. The PWRGD function is
masked during VID transitions to prevent false power fail
indications. Masking time is guaranteed to be at least
100usec over the full temperature range.
INTEL SpeedStep TECHNOLOGY
The LM27262 supports IST. See also respective Intel specs.
IST or Geyserville-III operation is a real-time dynamic switch-
ing of the CPU core voltage and frequency between multiple
performance modes.
DAC ACCURACY and V
REF SELECTION
The LM27262’s internal voltage reference is nominally
1.235V. Accuracy is ±0.9% or better at room temperature.
Due to the required precision of the VRD-10 specification,
the LM27262 was designed with the ability to use an external
precision reference. Since National Semiconductor’s preci-
sion 0.2% accurate voltage references have a 1.225V typical
output voltage, the LM27262 has a 10mV internal offset
switched in when REFINT selects an external reference.
This allows compensating for the 10mV difference between
the internal and external references. The LM27201 is the
recommended external reference for use with the LM27262.
STANDARD VID CODE OFFSET
Intel’s VRD-10 specification requires a “Standard Offset”.
This offset is typically 25mV but is subject to change with
future specification revisions. As such, the LM27262 has an
externally programmable offset. A resistor from the I
REF pin
to ground programs a precision current thru a resistor con-
nected between VPROG and VSTDOS pins. The recom-
mended nominal current value is 80A. The IREF pin forces
1.4V across the current programming resistor. The IREF
programming resistor value is therefore: R = 1.4V / 80A =
17.4k
.
The VPROG output is a buffered version of the internal DAC
output. The voltage drop between this pin and the VSTDOS
pin is equal to the IREF current times the value of the offset
resistor. For a 25mV offset and R
IREF equal to 17.4k
, the
offset resistor should be 309
. The error from using stan-
dard 1% resistor values is as follows: The source current can
20083423
FIGURE 3. Current Balancing Circuit
LM27262
www.national.com
14
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