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| 型号： | LM5051MAEVAL/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 12/23页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR LM5051MA |
| 标准包装： | 1 |
| 主要目的： | 电源管理，O 环控制器/低压侧 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LM5051 |
| 已供物品： | 板 |
SNVS702D – OCTOBER 2011 – REVISED MARCH 2013
The LM5051 is designed to regulate the MOSFET gate to source voltage if the voltage across the MOSFET
source and drain pins falls below the V SD(REG) voltage of 20 mV (typical). If the MOSFET current decreases to the
point that the voltage across the MOSFET falls below the V SD(REG) voltage regulation point of 12 mV (typical), the
GATE pin voltage will be decreased until the voltage across the MOSFET is regulated at 12 mV (typical). If the
drain to source voltage is greater thanV SD(REG) voltage the gate voltage will increase.
160
16
140
120
100
80
60
40
20
0
VGATE
VSD(REG)
Q1 = IRF7495PD F
VSD
14
12
10
8
6
4
2
0
0
1
2 3
4
5
ISD(A)
Figure 28. V SD and V GATE vs I LOAD with IRF7495PDF
When the power supply voltages are within a few milli-volts of each other, this regulation method ensures that
the load current transitions between them without any abrupt on and off oscillations. The current flowing through
the MOSFET in each OR-ing circuit depends on the R DS(ON) of the MOSFETs, how close the power supply
voltages are set, and the load regulation of the supplies.
If the MOSFET current reverses, possibly due to failure of the input supply, such that the voltage across the
LM5051 INN pin is 5 mV (typical) more positive than INP/VSS pin (V SD(REV) + Δ V SD(REV) ) the LM5051 will quickly
discharge the MOSFET gate through a strong GATE pin to INP/VSS pin discharge path. A reverse current
though the MOSFET is required to turn the gate drive off. If a single operating supply is removed from the OR-
ing array, the gate drive will not be discharged since there is no reverse current through the MOSFET to trip the
reverse comparator.
If the input supply fails abruptly, as would occur if the supply was shorted directly to ground, a reverse current
will temporarily flow through the MOSFET until the gate can be fully discharged. This reverse current is sourced
from the load capacitance and from the parallel connected supplies. The LM5051 responds to a voltage reversal
condition typically within 34 ns. The actual time required to turn off the MOSFET will depend on the charge held
by gate capacitance of the MOSFET being used. A MOSFET with 47 nF of effective gate capacitance can be
turned off in typically 90 ns. This fast turn-off time minimizes voltage disturbances at the output, as well as the
current transients from the redundant supplies.
OFF PIN
The OFF pin is used to disable the active OR-ing control circuitry, and to discharge the MOSFET Gate. The OFF
pin has an internal pull-down (4.6 μ A typical) which will, by default, keep the active OR-ing control circuitry
enabled. If the OFF pin function is not needed, this pin can be left open or connected to the INP/VSS pin. Pulling
the OFF pin above the V OFF(IH) threshold of 1.50V (typical) will disable the active OR-ing control circuitry and
discharge the MOSFET Gate. The V OFF threshold has a typical hysteresis of 20mV. It is recommended that the
OFF pin be pulled cleanly, and promptly, through the V OFF(IH) threshold region to prevent any aberrant behavior.
The OFF pin must not be pulled higher than 5.5V above the INP/VSS pin.
nFGD PIN
The nFGD pin is an open Drain output pin and is controlled by status of the Forward comparator. When the
voltage on INN pin is more negative than the V SD(TST) threshold voltage (285 mV typical) the nFGD pin will
conduct current to the INP/VSS pin. During normal Active OR-ing, when the MOSFET is ON, the INN pin voltage
should be less than approximately -100mV and the nFGD pin will be logic high. When the MOSFET is OFF and
current is flowing through the body diode of the MOSFET, the INN pin voltage will be approximately -600 mV and
the nFGD pin will be logic low.
12
Product Folder Links: LM5051
Copyright ? 2011–2013, Texas Instruments Incorporated
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