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参数资料
| 型号： | LMX2364TMX/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, PDSO24 |
| 封装： | TSSOP-24 |
| 文件页数： | 25/39页 |
| 文件大小： | 694K |
| 代理商： | LMX2364TMX/NOPB |
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Programming Description (Continued)
2.7.3 RF_PD — RF Synthesizer Power Down
Activation of the RF Synthesizer power down bit results in the disabling of the respective N divider and de-biasing of its respective
Fin inputs (to a high impedance state). The respective R divider functionality also becomes disabled when the power down bit is
activated. The OSCinRF pin reverts to a high impedance state when both RF and IF power down bits are asserted. Power down
forces the respective charge pump and phase comparator logic to a TRI-STATE condition. The MICROWIRE control register
remains active and capable of loading and latching in data during all of the power down modes.
Both synchronous and asynchronous power down modes are available with the LMX2364 in order to adapt to different types of
applications. The power down mode bit R6[8] is used to select between synchronous and asynchronous power down. The
MICROWIRE control register remains active and capable of loading and latching in data in either power down mode.
Synchronous Power down Mode: The RF synthesizer can be synchronously powered down by first setting the power down
mode bit HIGH (R6[8] = 1) and then asserting its power down bit (R4[23] = 1). The power down function is gated by the charge
pump. Once the power down bit is loaded, the part will go into power down mode upon the completion of a charge pump pulse
event.
Asynchronous Power down Mode: The RF synthesizer can be asynchronously powered down by first setting the power down
mode bit LOW (R6[8] = 0) and then asserting its power down bit (R4[23]] = 1). The power down function is NOT gated by the
charge pump. Once the power down bit is loaded, the part will go into power down mode immediately
LMX2364
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| LMX2370SLDX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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