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| 型号： | LP5521TMEV |
| 厂商： | National Semiconductor |
| 文件页数： | 11/44页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR LP5521 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | Q5109809 |
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BLOCK DIAGRAM
SNVS441F – JANUARY 2007 – REVISED FEBRUAY 2013
C FLY1
0.47 P F
C FLY2
0.47 P F
REF
TSD
VDD
POR
CLK
DET
CHARGE PUMP
1x/1.5x
VOUT
C OUT
C IN
BIAS
OSC
1 P F
1 P F
PROGRAM
MEMORY
Command based
VDD_ IO
ADDR_SEL0
ADDR_SEL1
PWM pattern generator
SCL
SDA
I 2 C
IDAC
VDD
MCU
EN
CLK_32K
INT
Control
D
A
VOUT
VOUT
R
G
TRIG
GPO
VOUT
B
LP5521
GND
Figure 21. Block Diagram
MODES OF OPERATION
RESET: In the RESET mode all the internal registers are reset to the default values. Reset is done always if
Reset Register (0DH) is written FFH or internal Power On Reset is activated. Power On Reset (POR) will
activate when supply voltage is connected or when the supply voltage V DD falls below 1.5V typ (0.8V min).
Once V DD rises above 1.5V, POR will inactivate and the chip will continue to the STANDBY mode.
CHIP_EN control bit is low after POR by default.
STANDBY: The STANDBY mode is entered if the register bit CHIP_EN or EN pin is LOW and Reset is not
active. This is the low power consumption mode, when all circuit functions are disabled. Registers can be
written in this mode if EN pin is high. Control bits are effective after start up.
STARTUP: When CHIP_EN bit is written high and EN pin is high, the INTERNAL STARTUP SEQUENCE
powers up all the needed internal blocks (V REF , Bias, Oscillator etc.). Startup delay is after setting EN pin
high is 1 ms (typ.). Startup delay after setting CHIP_EN to '1' is 500 μ s (typ.). If the chip temperature rises
too high, the Thermal Shutdown (TSD) disables the chip operation and the chip state is in STARTUP
mode, until no thermal shutdown event is present. (1)
NORMAL: During NORMAL mode the user controls the chip using the Control Registers. If EN pin is set low, the
CHIP_EN bit is reset to 0.
(1)
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T J = 150°C (typ.) and
disengages at T J = 130°C (typ.).
Copyright ? 2007–2013, Texas Instruments Incorporated
Product Folder Links: LP5521
11
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