参数资料
型号: LT1425IS#PBF
厂商: Linear Technology
文件页数: 14/20页
文件大小: 0K
描述: IC REG FLYBK ISOLATED .2A 16SOIC
标准包装: 50
类型: 回扫,隔离
输出数: 1
输入电压: 2.8 V ~ 20 V
PWM 型: 电流模式
频率 - 开关: 285kHz
电流 - 输出: 200mA
同步整流器:
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 管件
供应商设备封装: 16-SOIC
产品目录页面: 1327 (CN2011-ZH PDF)
LT1425
APPLICATIO N S I N FOR M ATIO N
) ) ) )
(V IN ? t ON ) 2
Min Power =
) ) ) )
1
I OUT(MIN) = (V IN ? t ON ) 2
) ) ) )
[V OUT ? (t EN + t ED )] 2
Min Power =
V F of this diode should therefore be included in R FB
calculations. Lot-to-lot and ambient temperature varia-
tions will show up as output voltage shift/drift.
Secondary Leakage Inductance
Leakage inductance on the transformer secondary
reduces the effective primary-to-secondary turns ratio
(N P /N S ) from its ideal value. This will increase the output
voltage target by a similar percentage. To the extent that
secondary leakage inductance is constant from part-to-
part, this can be accommodated by adjusting the R FB to
R REF resistor ratio.
Output Impedance Error
An additional error source is caused by transformer sec-
ondary current flow through the real life nonzero imped-
ances of the output rectifier, transformer secondary and
output capacitor. Because the secondary current only
flows during the off portion of the duty cycle, the effective
output impedance equals the “DC” lumped secondary
impedance times the inverse of the off duty cycle. If the
output load current remains relatively constant, or, in less
critical applications, the error may be judged acceptable
and the R FB value adjusted for nominal expected error. In
more demanding applications, output impedance error
may be minimized by the use of the load compensation
function (see Load Compensation).
V IN Sense Error
The LT1425 determines the size of the flyback pulse by
comparing the V SW signal to V IN , through R FB . This
comparison is not perfect, in the sense that an offset exists
between the sensing mechanism and the actual V IN . This
is expressed in the data sheet as V IN sense error. This error
is fixed in absolute millivolt terms relative to V OUT (with the
exception that it is reflected to V OUT by any nonunity
secondary-to-primary turns ratio).
MINIMUM LOAD CONSIDERATIONS
The LT1425 generally provides better low load perfor-
mance than previous generation switcher/controllers
utilizing indirect output voltage sensing techniques.
Specifically, it contains circuitry to detect flyback pulse
14
“collapse,” thereby supporting operation well into discon-
tinuous mode. Nevertheless, there still remain constraints
to ultimate low load operation. They relate to the minimum
switch ON time and the minimum enable time. Discontinu-
ous mode operation will be assumed in the following
theoretical derivations.
As outlined in the Operation section, the LT1425 utilizes a
minimum output switch ON time, t ON . This value can be
combined with expected V IN and switching frequency to
yield an expression for minimum delivered power.
1 f
2 L PRI
= (V OUT )(I OUT )
This expression then yields a minimum output current
constraint:
f
2 (L PRI )(V OUT )
where,
f = Switching frequency (nominally 285kHz)
L PRI = Transformer primary side inductance
V IN = Input voltage
V OUT = Output voltage
t ON = Output switch minimum ON time
An additional constraint has to do with the minimum
enable time. The LT1425 derives its output voltage infor-
mation from the flyback pulse. If the internal minimum
enable time pulse extends beyond the flyback pulse, loss
of regulation will occur. The onset of this condition can be
determined by setting the width of the flyback pulse equal
to the sum of the flyback enable delay, t ED , plus the
minimum enable time, t EN . Minimum power delivered to
the load is then:
1 f
2 L SEC
= (V OUT )(I OUT )
which yields a minimum output constraint:
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