- 您现在的位置：买卖IC网 > PDF目录14461 > LT1425IS#PBF (Linear Technology)IC REG FLYBK ISOLATED .2A 16SOIC PDF资料下载
参数资料
| 型号： | LT1425IS#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC REG FLYBK ISOLATED .2A 16SOIC |
| 标准包装： | 50 |
| 类型： | 回扫，隔离 |
| 输出数： | 1 |
| 输入电压： | 2.8 V ~ 20 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 285kHz |
| 电流 - 输出： | 200mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 16-SOIC |
| 产品目录页面： | 1327 (CN2011-ZH PDF) |
LT1425
OPERATIO N
) )
R OUT = ESR
) )
R OUT = ESR
regulation. See Applications Information section for fur-
ther details.
Enable Delay
When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans-
former primary side voltage waveform approximately rep-
resents the output voltage. This is partly due to rise time
on the V SW node, but more importantly due to transformer
leakage inductance. The latter causes a voltage spike on
the primary side not directly related to output voltage.
(Some time is also required for internal settling of the
feedback amplifier circuitry.)
In order to maintain immunity to these phenomena, a fixed
delay is introduced between the switch turn-off command
and the enabling of the feedback amplifier. This is termed
“enable delay.” In certain cases where the leakage spike is
not sufficiently settled by the end of the enable delay
period, regulation error may result. See Applications
Information section for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, that compares the flyback
voltage (R REF referred) to a fixed reference, nominally
80% of V BG . When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodates both continuous and discontinuous mode
operation.
Minimum Enable Time
The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time.” This prevents lock-up, especially when the output
voltage is abnormally low, e.g., during start-up. The mini-
mum enable time period ensures that the V C node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
the low load level at which output voltage regulation is lost.
See Applications Information section for details.
Effects of Variable Enable Period
It should now be clear that the flyback amplifier is enabled
only during a portion of the cycle time. This can vary from
the fixed “minimum enable time” described to a maximum
of roughly the OFF switch time minus the enable delay
time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and V C node slew rate.
LOAD COMPENSATION THEORY
The LT1425 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
transformer secondary and output capacitor. This has
been represented previously by the expression (I SEC )(ESR).
However, it is generally more useful to convert this expres-
sion to an effective output impedance. Because the sec-
ondary current only flows during the off portion of the duty
cycle, the effective output impedance equals the lumped
secondary impedance times the inverse of the OFF duty
cycle. That is,
1
DC OFF
where,
R OUT = Effective supply output impedance
ESR = Lumped secondary impedance
DC OFF = OFF duty cycle
Expressing this in terms of the ON duty cycle, remember-
ing DC OFF = 1 – DC,
1
1 – DC
DC = ON duty cycle
In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external R FB resistor
value adjusted to compensate for nominal expected error.
In more demanding applications, output impedance error
9
相关PDF资料 |
PDF描述 |
|---|---|
| HBM24DSXN | CONN EDGECARD 48POS DIP .156 SLD |
| RBC30DRAH-S734 | CONN EDGECARD 60POS .100 R/A PCB |
| HCM24DSXH | CONN EDGECARD 48POS DIP .156 SLD |
| HBM24DSXH | CONN EDGECARD 48POS DIP .156 SLD |
| HCM24DRXN | CONN EDGECARD 48POS DIP .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LT14-2-FP | 制造商:Thomas & Betts 功能描述:LT14-2 FOOD PROCESSINGOUTLET BOX 制造商:Thomas & Betts 功能描述:Fittings Gang Box 0.75inch Female Aluminum |
| LT1431 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Synchronous Rectifier Driver for Forward Converters |
| LT1431_10 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Programmable Reference |
| LT1431C | 制造商:LINER 制造商全称:Linear Technology 功能描述:Programmable Reference |
| LT1431CN8 | 功能描述:IC VREF SHUNT ADJ 8-PDIP RoHS:否 类别:集成电路 (IC) >> PMIC - 电压基准 系列:- 产品培训模块:Voltage Reference Basics 标准包装:100 系列:- 基准类型:旁路，精度 输出电压:4.096V 容差:±0.075% 温度系数:50ppm/°C 输入电压:- 通道数:1 电流 - 阴极:1µA 电流 - 静态:- 电流 - 输出:10mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。