参数资料
型号: LT1766HGN#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: 3 A SWITCHING REGULATOR, 228 kHz SWITCHING FREQ-MAX, PDSO16
封装: 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16
文件页数: 28/28页
文件大小: 284K
代理商: LT1766HGN#PBF
9
LT1766/LT1766-5
1766fb
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1766 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design. The 5V fixed output voltage part (LT1766-5) has
internal divider resistors and the FB pin is renamed SENSE,
connected directly to the output.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.
R
RVOUT
1
21 22
122
=
()
.
Table 1
OUTPUT
R1
% ERROR AT OUTPUT
VOLTAGE
R2
(NEAREST 1%)
DUE TO DISCREET 1%
(V)
(k
)(k)
RESISTOR STEPS
3
4.99
7.32
+ 0.32
3.3
4.99
8.45
– 0.43
5
4.99
15.4
– 0.30
6
4.75
18.7
+ 0.38
8
4.47
24.9
+ 0.20
10
4.32
30.9
– 0.54
12
4.12
36.5
+ 0.24
15
4.12
46.4
– 0.27
More Than Just Voltage Feedback
The feedback pin is used for more than just output
voltage sensing. It also reduces switching frequency and
current limit when output voltage is very low (see the
Frequency Foldback graph in Typical Performance Char-
acteristics). This is done to control power dissipation in
both the IC and in the external diode and inductor during
short-circuit conditions. A shorted output requires the
APPLICATIO S I FOR ATIO
WU
UU
switching regulator to operate at very low duty cycles,
and the average current through the diode and inductor
is equal to the short-circuit current limit of the switch
(typically 2A for the LT1766, folding back to less than
1A). Minimum switch on time limitations would prevent
the switcher from attaining a sufficiently low duty cycle
if switching frequency were maintained at 200kHz, so
frequency is reduced by about 5:1 when the feedback pin
voltage drops below 0.8V (see Frequency Foldback graph).
This does not affect operation with normal load condi-
tions; one simply sees a gear shift in switching frequency
during start-up as the output voltage rises.
In addition to lower switching frequency, the LT1766 also
operates at lower switch current limit when the feedback
pin voltage drops below 0.6V. Q2 in Figure 2 performs this
function by clamping the VC pin to a voltage less than its
normal 2.1V upper clamp level. This
foldback current limit
greatly reduces power dissipation in the IC, diode and in-
ductor during short-circuit conditions. External synchro-
nization is also disabled to prevent interference with fold-
back operation. Again, it is nearly transparent to the user
under normal load conditions. The only loads that may be
affected are current source loads which maintain full load
current with output voltage less than 50% of final value. In
these rare situations the feedback pin can be clamped above
0.6V with an external diode to defeat foldback current limit.
Caution: clamping the feedback pin means that frequency
shifting will also be defeated, so a combination of high in-
put voltage and dead shorted output may cause the LT1766
to lose control of current limit.
The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
conduct current and reduces frequency at the rate of
approximately 1.4kHz/
A. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pull 115
A out of the FB pin with 0.44V on the pin (RDIV
≤ 3.8k). The net result is that reductions in frequency and
current limit are affected by output voltage divider imped-
ance. Although divider impedance is not critical, caution
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