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参数资料
| 型号： | LT1941EFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI CONFIG TRPL 28TSSOP |
| 标准包装： | 50 |
| 类型： | 降压（降压），升压（升压），反相，Sepic |
| 输出类型： | 可调式 |
| 输出数： | 3 |
| 输出电压： | 1.25 V ~ 40 V |
| 输入电压： | 3.5 V ~ 25 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
LT1941
APPLICATIONS INFORMATION
Table 5. Converter Equivalent Model Parameters
single capacitor providing soft-start. The internal current
STEP-DOWN1 STEP-DOWN2
BOOST
INVERTER
sources will charge these pins to ~2V.
V FB
R O
g ma
g mp
0.628V
500kΩ
1700μmho
5mho
0.628V
500kΩ
1700μmho
3.6mho
1.25
500kΩ
800μmho
V IN ? 5mho
V OUT
1.24
500kΩ
800μmho
V IN ? 5mho
–|V OUT |
The RUN/SS pins provide a soft-start function that limits
peak input current to the circuit during start-up. This helps
to avoid drawing more current than the input source can
supply or glitching the input supply when the LT1941 is
enabled. The RUN/SS pins do not provide an accurate
delay to start or an accurately controlled ramp at the
LT1941
output voltage, both of which depend on the output ca-
CURRENT MODE
POWER STAGE
g mp
ERROR
AMPLIFIER
V SW
FB
R1
C PL
OUTPUT
pacitance and the load current. However, the power good
indicators can be used to sequence the three outputs, as
described below.
GND
V C
500k
g ma
V FB
ESR
+
C1
C1
POWER GOOD INDICATORS
The PGOOD pin is the open-collector output of an internal
R C
C C
C F
R2
POLYMER
OR
TANTALUM
CERAMIC
comparator. PGOOD remains low until the FB pin is within
10% of the ?nal regulation voltage. Tie the PGOOD to any
supply with a pull-up resistor that will supply less than
200μA. Note that this pin will be open when the LT1941
1941 F05
Figure 5. Model for Loop Response
SOFT-START AND SHUTDOWN
The RUN/SS (Run/Soft-Start) pins are used to place the
individual switching regulators and the internal bias cir-
cuits in shutdown mode. They also provide a soft-start
function. To shut down a regulator, pull its RUN/SS pin to
ground with an open drain or collector. If all three RUN/SS
pins are pulled to ground, the LT1941 enters its shutdown
mode with all regulators off and quiescent current reduced
to ~50mA. Internal 2μA current sources pull up on each
pin. If any RUN/SS pin reaches ~0.6V, the internal bias
circuits start and the quiescent currents increase to their
nominal levels.
If a capacitor is tied from the RUN/SS pin to ground, then
the internal pull-up current will generate a voltage ramp on
this pin. This voltage clamps the V C pin, limiting the peak
switch current and therefore input current during start-up.
A good value for the soft-start capacitor is C OUT /10,000,
where C OUT is the value of the output capacitor.
The RUN/SS pins can be left ?oating if the shutdown
is in shutdown mode (all three RUN/SS pins at ground)
regardless of the voltage at the FB pin. PGOOD is valid
when the LT1941 is enabled (any RUN/SS pin is high) and
V IN is greater than ~3.5V.
The 5GOOD and 12GOOD pins are also open-collector
outputs of internal comparators. The 5GOOD pin remains
low until the input is within 10% of 5V. Tie the 5GOOD and
12GOOD pins to any supply with a pull-up resistor that will
supply less than 100μA. The 12GOOD pin remains low until
the input is within 10% of 12V. The 5GOOD and 12GOOD
pins are valid as long as V IN is greater than 1.1V. Both the
5GOOD and 12GOOD pins will sink current when the part
is in shutdown, independent of the voltage at V IN .
Output Sequencing
The PG and RUN/SS pins can be used to sequence the
three outputs. Figure 6 shows several circuits to do this.
The techniques shown to sequence two channels can be
extended to sequence the third. In each case channel 1
starts ?rst. Note that these circuits sequence the outputs
during start-up. When shut down the three channels turn
off simultaneously.
feature is not used. They can also be tied together with a
1941fb
17
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