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| 型号： | LT1941EFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/24页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI CONFIG TRPL 28TSSOP |
| 标准包装： | 50 |
| 类型： | 降压（降压），升压（升压），反相，Sepic |
| 输出类型： | 可调式 |
| 输出数： | 3 |
| 输出电压： | 1.25 V ~ 40 V |
| 输入电压： | 3.5 V ~ 25 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
LT1941
BLOCK DIAGRAM
The LT1941 is a constant frequency, current mode, triple
output regulator with internal power switches. The three
regulators share common circuitry including input source,
voltage reference and oscillator, but are otherwise inde-
pendent. Operation can be best understood by referring
to the Block Diagram.
If the RUN/SS pins are tied to ground, the LT1941 is shut
down and draws 50μA from the input source tied to V IN .
Internal 2μA current sources charge external soft-start
capacitors, generating voltage ramps at these pins. If any
of the RUN/SS pins exceed 0.6V, the internal bias circuits
turn on, including the internal regulator, reference and
1.1MHz master oscillator. Each switching regulator will
only begin to operate when its corresponding RUN/SS pin
reaches ≈1V. The master oscillator generates three clock
signals, with the two signals for the step-down regulators
out of phase by 180°.
The three switchers are current mode regulators. Instead
of directly modulating the duty cycle of the power switch,
the feedback loop controls the peak current in the switch
during each cycle. Compared to voltage mode control, cur-
rent mode control improves loop dynamics and provides
cycle-by-cycle current limit.
The Block Diagram shows only one of the two step-down
switching regulators. A pulse from the slave oscillator
sets the RS ?ip-?op and turns on the internal NPN bipo-
lar power switch. Current in the switch and the external
inductor begins to increase. When this current exceeds a
level determined by the voltage at V C , current comparator
C1 resets the ?ip-?op, turning off the switch. The current
in the inductor ?ows through the external Schottky diode
and begins to decrease. The cycle begins again at the next
pulse from the oscillator. In this way, the voltage on the
V C pin controls the current through the inductor to the
output. The internal error ampli?er regulates the output
voltage by continually adjusting the V C pin voltage. The
threshold for switching on the V C pin is ≈1V and an active
clamp of 1.7V limits the output current. The RUN/SS pin
voltage also clamps the V C pin voltage. As the internal
current source charges the external soft-start capacitor,
the current limit increases slowly. An internal op amp
allows the part to regulate negative voltages using only
Each switcher contains an extra, independent oscillator to
perform frequency foldback during overload conditions.
This slave oscillator is normally synchronized to the master
oscillator. A comparator senses when V FB is less than 50%
of its regulated value and switches the regulator from the
master oscillator to a slower slave oscillator. The V FB pin is
less than 50% of its regulated value during start-up, short
circuit and overload conditions. Frequency foldback helps
limit switch current under these conditions.
The switch drivers for SW1 and SW2 operate either
from V IN or from the BOOST pin. An external capacitor
and diode are used to generate a voltage at the BOOST
pin that is higher than the input supply. This allows the
driver to saturate the internal bipolar NPN power switch
for ef?cient operation.
The BIAS1 pin allows the internal circuitry to draw its
current from a lower voltage supply than the input, also
reducing power dissipation and increasing ef?ciency. If
the voltage on the BIAS1 pin falls below 2.35V, then its
quiescent current will ?ow from V IN .
The BIAS2 pin allows the driver for SW3 to draw its
current from a lower voltage supply than the input. This
reduces power dissipation within the part and increases
ef?ciency. If the voltage on the BIAS2 pin falls below ≈2V,
then SW3 will lock out and will not be able to turn on until
BIAS2 rises above ≈2.1V.
A power good comparator trips when the FB pin is at
91% of its regulated value. The PGOOD output is an
open-collector transistor that is off when the output is in
regulation, allowing an external resistor to pull the PGOOD
pin high. Power good is valid when the LT1941 is enabled
and V IN > 3.5V.
Input power good comparators monitor the input supply.
The 5GOOD and 12GOOD pins are open-collector outputs
of internal comparators. The 5GOOD pin remains low until
the input is within 10% of 5V. The 12GOOD pin remains
low until the input is within 10% of 12V. The 5GOOD and
12GOOD pins are valid as long as V IN is greater than
1.1V. Both the 5GOOD and 12GOOD pins will sink current
when the part is in shutdown, independent of the voltage
at V IN.
two external resistors.
1941fb
8
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