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参数资料
| 型号： | LT1941EFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI CONFIG TRPL 28TSSOP |
| 标准包装： | 50 |
| 类型： | 降压（降压），升压（升压），反相，Sepic |
| 输出类型： | 可调式 |
| 输出数： | 3 |
| 输出电压： | 1.25 V ~ 40 V |
| 输入电压： | 3.5 V ~ 25 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
LT1941
APPLICATIONS INFORMATION
In Figure 6a, a larger capacitor on RUN/SS2 delays channel
2 with respect to channel 1. The soft-start capacitor on
RUN/SS2 should be at least twice the value of the capacitor
on RUN/SS1. A larger ratio may be required, depending
on the output capacitance and load on each channel. Make
sure to test the circuit in the system before deciding on
?nal values for these capacitors.
The circuit in Figure 6b requires the fewest components,
with both channels sharing a single soft-start capacitor.
The power good comparator of channel 1 disables chan-
nel 2 until output 1 is in regulation.
For independent control of channel 2, use the circuit in
Figure 6c. The capacitor on RUN/SS1 is smaller than the
capacitor on RUN/SS2. This allows the LT1941 to start up
and enable its power good comparator before RUN/SS2
gets high enough to allow channel 2 to start switching.
Channel 2 only operates when it is enabled with the external
control signals and output 1 is in regulation.
The circuit in Figure 6a leaves both power good indica-
tors free. However, the circuits in Figures 6b and 6c have
another advantage. As well as sequencing the two outputs
at start-up, they also disable channel 2 if output 1 falls
out of regulation (due to a short circuit or a collapsing
input voltage).
Finally, be aware that the circuit in Figure 6d does not
work , because the power good comparators are disabled
in shutdown.
PCB LAYOUT
For proper operation and minimum EMI, care must be taken
during printed circuit board (PCB) layout. Figure 7 shows
the high current paths in the step-down regulator circuit.
Note that in the step-down regulators large, switched
currents ?ow in the power switch, the catch diode and
the input capacitor. In the inverter/boost regulator large,
switched currents ?ow through the power switch, the
switching diode, and either the output capacitor in boost
con?guration, or the tank capacitor in the inverter con-
?guration. The loop formed by these components should
be as small as possible. Place these components, along
with the inductor and output capacitor, on the same side
of the circuit board and connect them on that layer. Place
a local, unbroken ground plane below these components
and tie this ground plane to system ground at one loca-
tion, ideally at the ground terminal of the output capacitor
C2. Additionally, keep the SW and BOOST nodes as small
as possible.
RUN/SS1
RUN/SS1
V C2
OFF ON
1nF
LT1941
RUN/SS2
GND
OFF ON
1nF
LT1941
RUN/SS2
GND
PG1
2.2nF
(6a) Channel 2 is Delayed
RUN/SS1
(6b) Fewest Components
RUN/SS1
OFF ON
1nF
LT1941
OFF ON
1nF
LT1941
PG1
RUN/SS2
GND
PG1
RUN/SS2
GND
OFF2 ON2
1.5nF
1.5nF
1941 F06
(6c) Independent Control of Channel 2
(6d) Doesn't Work !
Figure 6. Several Methods of Sequencing Two Ouputs. Channel 1 Starts First
1941fb
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