参数资料
型号: LT1943EFE#TRPBF
厂商: Linear Technology
文件页数: 8/20页
文件大小: 0K
描述: IC REG SW QUAD TFT LCD 28-TSSOP
标准包装: 2,000
应用: 转换器,TFT,LCD
输入电压: 4.5 V ~ 22 V
输出数: 4
输出电压: 1.25 V ~ 40 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 28-TSSOP 裸露焊盘
包装: 带卷 (TR)
LT1943
PI FU CTIO S
SW3 (Pin 21): This is the collector of the internal NPN
bipolar power transistor for switching regulator 3. Mini-
mize metal trace area at this pin to keep EMI down.
BIAS (Pin 22): The BIAS pin is used to improve efficiency
when operating at higher input voltages. Connecting this
pin to the output of switching regulator 1 forces most of
the internal circuitry to draw its operating current from
V LOGIC rather than V IN . The drivers of switches 2, 3 and 4
are supplied by BIAS. Switches 2, 3 and 4 will not switch
until the BIAS pin reaches approximately 2.8V. BIAS must
be tied to V LOGIC .
PGOOD (Pin 23): Power Good Comparator Output. This is
the open collector output of the power good comparator
and can be used in conjunction with an external P-Channel
MOSFET to provide output disconnect for AV DD as shown
in the 5V Input, Quad Output TFT-LCD Power Supply on
the last page of the data sheet. When switcher 2’s output
reaches approximately 90% of its programmed voltage,
PGOOD will be pulled to ground. This will pull down on the
gate of the MOSFET, connecting AV DD . A 100k pull-up
resistor between the source and gate of the P-channel
MOSFET keeps it off when switcher 2’s output is low.
E3 (Pin 24): This is switching regulator 3’s output and the
emitter of the output disconnect PNP. Tie the output
capacitor and resistor divider here.
C T (Pin 25): Timing Capacitor Pin. This is the input to the
V ON timer and programs the time delay from all four
feedback pins reaching 1.125V to V ON turning on. The C T
capacitor value can be set using the equation C = (20 μ A ?
t DELAY )/1.1V.
V ON (Pin 26): This is the delayed output for switching
regulator 3. V ON reaches its programmed voltage after the
internal C T timer times out. Protection circuitry ensures
V ON is disabled if any of the four outputs are more than
10% below normal voltage.
SW2 (Pins 27, 28): The SW2 pins are the collector of the
internal NPN bipolar power transistor for switching regu-
lator 2. These pins must be tied together. Minimize trace
area at these pins to keep EMI down.
1943fa
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