参数资料
| 型号： | LT3431IFE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A 16TSSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.2 V ~ 48 V |
| 输入电压： | 5.5 V ~ 60 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-TSSOP-EP |
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LT3431
APPLICATIO S I FOR ATIO
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT3431 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the second part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.
R 1 = R 2 ( V OUT ? 1 . 22 )
1 . 22
short-circuit current limit of the switch (typically 4A for the
LT3431, folding back to less than 2A). Minimum switch on
time limitations would prevent the switcher from attaining
a sufficiently low duty cycle if switching frequency were
maintained at 500kHz, so frequency is reduced by about
5:1 when the feedback pin voltage drops below 0.8V (see
Frequency Foldback graph). This does not affect operation
with normal load conditions; one simply sees a gear shift
in switching frequency during start-up as the output
voltage rises.
In addition to lower switching frequency, the LT3431 also
operates at lower switch current limit when the feedback
pin voltage drops below 0.6V. Q2 in Figure 2 performs this
function by clamping the V C pin to a voltage less than its
normal 2.1V upper clamp level. This foldback current limit
greatly reduces power dissipation in the IC, diode and in-
ductor during short-circuit conditions. External synchro-
nization is also disabled to prevent interference with fold-
back operation. Again, it is nearly transparent to the user
under normal load conditions. The only loads that may be
Table 1
OUTPUT
VOLTAGE
(V)
3
3.3
5
6
8
10
12
15
R2
(k ? )
4.99
4.99
4.99
4.75
4.47
4.32
4.12
4.12
R1
(NEAREST 1%)
(k ? )
7.32
8.45
15.4
18.7
24.9
30.9
36.5
46.4
% ERROR AT OUTPUT
DUE TO DISCREET 1%
RESISTOR STEPS
+ 0.32
– 0.43
– 0.30
+ 0.40
+ 0.20
– 0.54
+ 0.24
– 0.27
affected are current source loads which maintain full load
current with output voltage less than 50% of final value. In
these rare situations the feedback pin can be clamped above
0.6V with an external diode to defeat foldback current limit.
Caution: clamping the feedback pin means that frequency
shifting will also be defeated, so a combination of high in-
put voltage and dead shorted output may cause the LT3431
to lose control of current limit.
The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
More Than Just Voltage Feedback
The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
This is done to control power dissipation in both the IC and
in the external diode and inductor during short-circuit
conditions. A shorted output requires the switching regu-
lator to operate at very low duty cycles, and the average
current through the diode and inductor is equal to the
conduct current and reduces frequency at the rate of
approximately 3.5kHz/ μ A. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pull 115 μ A out of the FB pin with 0.44V on the pin (R DIV
≤ 3.8k). The net result is that reductions in frequency and
current limit are affected by output voltage divider imped-
ance. Although divider impedance is not critical, caution
should be used if resistors are increased beyond the
suggested values and short-circuit conditions can possi-
bly occur with high input voltage. High frequency pickup
sn3431 3431fs
8
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相关代理商/技术参数 |
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| LT3433 | 制造商:LINER 制造商全称:Linear Technology 功能描述:High Voltage Step-Up/Step-Down DC/DC Converter |
| LT3433_1 | 制造商:LINER 制造商全称:Linear Technology 功能描述:High Voltage Step-Up/Step-Down DC/DC Converter |
| LT3433EFE | 功能描述:IC REG BUCK BST ADJ 0.5A 16TSSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:2,500 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V，1.5V，1.8V，2.5V 输入电压:2.7 V ~ 20 V PWM 型:- 频率 - 开关:- 电流 - 输出:50mA 同步整流器:是 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 包装:带卷 (TR) 供应商设备封装:10-MSOP 裸露焊盘 |
| LT3433EFE#PBF | 功能描述:IC REG BUCK BST ADJ 0.5A 16TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
| LT3433EFE#TR | 功能描述:IC REG BUCK BST ADJ 0.5A 16TSSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:2,500 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V，1.5V，1.8V，2.5V 输入电压:2.7 V ~ 20 V PWM 型:- 频率 - 开关:- 电流 - 输出:50mA 同步整流器:是 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 包装:带卷 (TR) 供应商设备封装:10-MSOP 裸露焊盘 |
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