参数资料
型号: LT3487EDD#PBF
厂商: Linear Technology
文件页数: 10/16页
文件大小: 0K
描述: IC REG BOOST INV ADJ 10DFN
标准包装: 121
类型: 升压(升压),反相
输出类型: 可调式
输出数: 1
输出电压: 1.23 V ~ 28 V
输入电压: 2.3 V ~ 16 V
PWM 型: 电流模式
频率 - 开关: 2MHz
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 10-DFN(3x3)
产品目录页面: 1331 (CN2011-ZH PDF)
LT3487
APPLICATIO S I FOR ATIO
R 1 = ? POS
Setting the Output Voltages
The LT3487 has an accurate internal feedback resistor
that is trimmed to set the feedback currents to 25μA for
each channel. Only one resistor is needed to set the output
voltage for each channel. The output voltage can be set
according to the following formulas:
? V – 1 . 23 ?
?
? 25 μA ?
Start Sequencing
The LT3487 also has internal sequencing circuitry that
inhibits the negative channel from operating until the
feedback voltage of the boost channel reaches about 1.1V
(87% of the ?nal voltage), ensuring that the sum of the
two outputs is always positive.
There are two ways in which the negative channel may
start up, depending on the size of the soft-start capacitor.
If there is no soft-start capacitor, or a very small capacitor,
R 2 =
– V NEG
25 μA
then the negative channel will start up when the positive
output reaches 87% of its ?nal value. If a large enough
soft-start capacitor is used, then the RUN/SS voltage will
In order to maintain accuracy, high precision resistors are
preferred (1% is recommended).
Soft-Start
The LT3487 has a single soft-start control for both chan-
nels. The RUN/SS pin is fed by a 1.4μA current source.
The soft-start ramp can be programmed by connecting a
capacitor from the RUN/SS pin to ground. An open-drain
transistor should be used to pull the pin low to shut down
the LT3487. Once the transistor stops sinking the 1.4μA,
the capacitor begins to charge. The chip starts up when
the RUN/SS pin charges to 160mV. The V CP node voltage
follows the RUN/SS voltage as it continues to ramp up
to ensure slow start-up on the positive channel. The V CN
node follows the ramp voltage, down a V BE . This ensures
that the negative channel starts up after the positive, but
still has a slow ramping output to avoid large start-up
currents.
continue to clamp the negative channel past the point
where the positive channel is in regulation. Figure 3 shows
the start-up sequencing without soft-start, with a small
soft-start capacitor, and a large soft-start capacitor.
Output Disconnect
The output disconnect uses a PNP transistor with circuitry
that varies the base current such that the transistor is
consistently at the edge of saturation, thus yielding the
best compromise between V CE(SAT) and low quiescent
current. To remain stable, this circuit requires a bypass
capacitor connected between the V POS pin and the CAP pin
or between the V POS pin and ground. A ceramic capacitor
with a value of at least 0.1μF is a good choice. Figure 4
shows that the PNP can support load currents of 50mA
with a V CE less than 210mV. The disconnect transistor is
current limited to provide a maximum of 155mA in short
circuit.
V RUN/SS
2V/DIV
I IN
1A/DIV
V POS
10V/DIV
V NEG
10V/DIV
V RUN/SS
2V/DIV
I IN
500mA/DIV
V POS
10V/DIV
V NEG
10V/DIV
V RUN/SS
2V/DIV
I IN
200mA/DIV
V POS
10V/DIV
V NEG
10V/DIV
500 μ s/DIV
3487 F03a
2ms/DIV
3487 F03b
10ms/DIV
3487 F03c
Figure 3a. V RUN/SS , V POS , V NEG ,
I IN with No Soft-Start Capacitor
Figure 3b. V RUN/SS , V POS , V NEG ,
I IN with a 10nF Soft-Start Capacitor
Figure 3c. V RUN /SS, V POS , V NEG , I IN
with a 100nF Soft-Start Capacitor
3487f
10
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