参数资料
型号: LT3579EFE#PBF
厂商: Linear Technology
文件页数: 17/40页
文件大小: 0K
描述: IC REG MULTI CONFIG SYNC 20TSSOP
标准包装: 74
类型: 升压(升压),反相,回扫,Sepic
输出数: 1
输入电压: 2.5 V ~ 16 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.5MHz
电流 - 输出: 6A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
包装: 管件
供应商设备封装: 20-TSSOP-EP
LT3579/LT3579-1
APPLICATIONS INFORMATION
Inverting Topology Specific Layout Guidelines
? Keep ground return path from the cathode of D1 (to
chip) separated from output capacitor C OUT ’s ground
return path (to chip) in order to minimize switching
noise coupling into the output. Notice the separate
ground return for D1’s cathode in Figure 11.
? Keep length of loop (high speed switching path)
governing switch, flying capacitor C1, diode D1, and
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
THERMAL CONSIDERATIONS
For the LT3579 to deliver its full output power, it is imp-
erative that a good thermal path be provided to dissipate
the heat generated within the package. This can be
accomplished by taking advantage of the thermal pad on
the underside of the IC. It is recommended that multiple
vias in the printed circuit board be used to conduct heat
away from the IC and into a copper plane with as much
area as possible.
Power & Thermal Calculations
Power dissipation in the LT3579 chip comes from four
primary sources: switch I 2 R loss, NPN base drive loss
(AC), NPN base drive loss (DC), and additional V IN pin
current. These formulas assume continuous mode
operation, so they should not be used for calculating
thermal losses or efficiency in discontinuous mode or at
light load currents.
VIAS TO GROUND PLANE REQUIRED TO IMPROVE
THERMAL PERFORMANCE
GND
1
2
3
4
21
20
19
18
17
SYNC
SHDN
C IN
5
6
7
16
15
14
CLKOUT
A
8
13
B
9
12
V IN
+
10
11
C OUT
L1
L2
C1
D1
V OUT
+
35791 F10
A– RETURN C IN AND L2 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE C IN AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B– RETURN C OUT GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE C OUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2 –MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE.
Figure 10. Suggested Component Placement for SEPIC Topology in FE20 Package
35791f
17
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