参数资料
型号: LT3579EFE#PBF
厂商: Linear Technology
文件页数: 27/40页
文件大小: 0K
描述: IC REG MULTI CONFIG SYNC 20TSSOP
标准包装: 74
类型: 升压(升压),反相,回扫,Sepic
输出数: 1
输入电压: 2.5 V ~ 16 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.5MHz
电流 - 输出: 6A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
包装: 管件
供应商设备封装: 20-TSSOP-EP
LT3579/LT3579-1
APPENDIX
R GATE
R GATE + 2k ?
933μA ? R GATE if V GATE > 2V
Table 6 shows a list of several ceramic capacitor man-
ufacturers. Consult the manufacturers for detailed infor-
mation on their entire selection of ceramic parts.
Table 6. Ceramic Capacitor Manufacturers
TDK www.tdk.com
Murata www.murata.com
Taiyo Yuden www.t-yuden.com
PMOS SELECTION
An external PMOS, controlled by the LT3579’s GATE pin,
can be used to facilitate input or output disconnect. The
GATE pin turns on the PMOS gradually during start-up
(see Soft-Start of External PMOS in the Operation section),
and turns the PMOS off when the LT3579 is in shutdown
or in fault.
The use of the external PMOS, controlled by the GATE pin,
is particularly beneficial when dealing with unintended
output shorts in a boost regulator. In a conventional boost
regulator, the inductor, Schottky diode, and power switches
are susceptible to damage in the event of an output short
to ground. Using an external PMOS in the boost regulator’s
power path (path from V IN to V OUT ) controlled by the GATE
pin, will serve to disconnect the input from the output
when the output has a short to ground, thereby helping
save the IC, and the other components in the power path
from damage.
The PMOS chosen must be capable of handling the
maximum input or output current depending on whether
the PMOS is used at the input (see Figure 12) or the output
(see Figure 13).
Ensure that the PMOS is biased with enough source to gate
voltage (V SG ) to enhance the device into the triode mode
of operation. The higher the V SG voltage that biases the
PMOS, the lower the R DSON of the PMOS, thereby lowering
power dissipation in the device during normal operation,
as well as improving the efficiency of the application in
which the PMOS is used. The following equations show
the relationship between R GATE (see Block Diagram) and
the desired V SG that the PMOS is biased with:
?
? V S if V GATE < 2V
V SG = ?
?
?
When using a PMOS, it is advisable to configure the specific
application for undervoltage lockout (see the Operations
section). The goal is to have V IN get to a certain minimum
voltage where the PMOS has sufficient headroom to attain
a high enough V SG , which prevents it from entering the
saturation mode of operation during start-up.
Figure 6 shows the PMOS connected in series with the
output to act as an output disconnect during a fault
condition. The Schottky diode from the V IN pin to the GATE
pin is optional and helps turn off the PMOS quicker in the
event of hard shorts. The resistor from V IN to the SHDN
pin sets a UVLO of 4V for this application.
Connecting the PMOS in series with the output offers certain
advantages over connecting it in series with the input:
? Since the load current is always less than the input
current for a boost converter, the current rating of the
PMOS goes down when connected in series with the
output as opposed to the input.
? A PMOS in series with the output can be biased with
a higher overdrive voltage than a PMOS used in series
with the input, since V OUT > V IN . This higher overdrive
results in a lower R DSON for the PMOS, thereby improving
the efficiency of the regulator.
In contrast, an input connected PMOS works as a simple
hot-plug controller (covered in more detail in the Hot-Plug
section). The input connected PMOS also functions as an
inexpensive means of protecting against multiple output
shorts in boost applications that synchronize the LT3579
with other compatible ICs (see Figure 12).
35791f
27
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