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参数资料
| 型号： | LTC2256IUJ-14#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| 封装： | 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40 |
| 文件页数： | 8/32页 |
| 文件大小： | 1546K |
| 代理商： | LTC2256IUJ-14#PBF |
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LTC2258-14
LTC2257-14/LTC2256-14
16
225814fa
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
PIN FUNCTIONS
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overow or underow has occurred.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1–/D0_1+ to D12_13–/D12_13+ (Pins 17/18, 19/20,
21/22, 23/24, 29/30, 31/32, 33/34): Double Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (D0, D2, D4,
D6, D8, D10, D12) appear when CLKOUT+ is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–/OF+ (Pins 35/36): Over/Under Flow Digital Output. OF+
is high when an overow or underow has occurred.
DIFF
REF
AMP
REF
BUF
2.2μF
0.1μF
INTERNAL CLOCK SIGNALS
REFH
REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.25V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC+
REFH
REFL
ENC–
SHIFT REGISTER
AND CORRECTION
SDO
CS
OGND
OF
OVDD
D13
CLKOUT–
CLKOUT+
D0
225814 F01
INPUT
S/H
SENSE
VREF
AIN
–
AIN
+
1μF
VCM
0.1μF
VDD/2
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
MODE
CONTROL
REGISTERS
SCK
PAR/SER
SDI
VDD
GND
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2257CUJ-14#PBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2257IUJ-14#PBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2259CUJ-16#PBF | PROPRIETARY METHOD ADC, PQCC40 |
| LTC2259IUJ-16#PBF | PROPRIETARY METHOD ADC, PQCC40 |
| LTC2259CUJ-16#TRPBF | PROPRIETARY METHOD ADC, PQCC40 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2256IUJ-14-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 65/40/25Msps Ultralow Power 1.8V ADCs |
| LTC2256UJ-12 | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 65/40/2 5Msps Ultralow Power 1.8V ADCs |
| LTC2256UJ-14 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 65/40/25Msps Ultralow Power 1.8V ADCs |
| LTC2257-12 | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 65/40/2 5Msps Ultralow Power 1.8V ADCs |
| LTC2257-14 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 65/40/25Msps Ultralow Power 1.8V ADCs |
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