参数资料
| 型号： | LTC3412IFE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 16TSSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 5 V |
| 输入电压： | 2.63 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 950kHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-TSSOP-EP |
LTC3412
APPLICATIO S I FOR ATIO
The junction temperature, T J , is given by:
First, calculate the timing resistor:
T J = T A + T R
where T A is the ambient temperature.
R OSC =
3 . 23 ? 10 11
1 ? 10 6
? 10 k = 313 k
As an example, consider the LTC3412 in dropout at an
input voltage of 3.3V, a load current of 2.5A and an
ambient temperature of 70 ° C. From the typical perfor-
Use a standard value of 309k. Next, calculate the inductor
value for about 40% ripple current at maximum V IN :
L = ? ? ? 1 ?
? = 1 . 01 μ H
mance graph of switch resistance, the R DS(ON) of the P-
channel switch at 70 ° C is approximately 97m Ω . There-
fore, power dissipated by the part is:
? 2 . 5 V ? ?
? ( 1 MHz )( 1 A ) ? ?
2 . 5 V ?
4 . 2 V ?
P D = (I LOAD2 )(R DS(ON) ) = (2.5A) 2 (97m Ω ) = 0.61W
For the TSSOP package, the θ JA is 37.6 ° C/W. Thus the
Using a 1 μ H inductor, results in a maximum ripple current
of:
? ? ? 1 ?
Δ I L = ?
? = 1 . 01 A
junction temperature of the regulator is:
T J = 70 ° C + (0.61W)(37.6 ° C/W) = 93 ° C
? 2 . 5 V ? ?
? ( 1 MHz )( 1 μ H ) ?
2 . 5 V ?
4 . 2 V ?
which is below the maximum junction temperature of
125 ° C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R DS(ON) ).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
C OUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. In this application,
two tantalum capacitors will be used to provide the bulk
capacitance and a ceramic capacitor in parallel to lower the
total effective ESR. For this design, two 100 μ F tantalum
capacitors in parallel with a 10 μ F ceramic capacitor will be
used. C IN should be sized for a maximum current rating of:
I RMS = ( ) ?
? 2 . 5 V ? 4 . 2 V
?
several cycles to respond to a step in load current. When
a load step occurs, V OUT immediately shifts by an amount
equal to Δ I LOAD (ESR), where ESR is the effective series
2 . 5 A
? 4 . 2 V ? 2 . 5 V
? 1 = 1 . 23 A RMS
I BURST = ( ) ?
? 3 . 75 V ?
resistance of C OUT . ΔI LOAD also begins to charge or
discharge C OUT generating a feedback error signal used by
the regulator to return V OUT to its steady-state value.
During this recovery time, V OUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I TH pin external components and output capaci-
tor shown in Figure 1 will provide adequate compensation
for most applications.
Design Example
As a design example, consider using the LTC3412 in an
application with the following specifications: V IN = 2.7V to
4.2V, V OUT = 2.5V, I OUT(MAX) = 2.5A, I OUT(MIN) = 10mA, f
Decoupling the PV IN and SV IN pins with a 22 μ F ceramic
capacitor and a 220 μ F tantalum capacitor is adequate for
most applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2 and R3. The
voltage on the MODE pin will be set to 0.32V by the resistor
divider consisting of R2 and R3. A burst clamp voltage of
0.32V will set the minimum inductor current, I BURST , as
follows:
0 . 32 V ? 0 . 2 V ? = 563 mA
? 0 . 8 V ?
= 1MHz. Because efficiency is important at both high and
low load current, Burst Mode operation will be utilized.
3412fb
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