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| 型号： | LTC3447EDD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 0.6A 10DFN |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.69 V ~ 2.05 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 600mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-DFN（3x3） |
LTC3447
OPERATIO
The START and STOP Commands
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmission
with a START command by transitioning SDA from high
to low while SCL is high. When the master has ?nished
communicating with the slave, it issues a STOP command
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge signal (LOW
active) is generated by the slave lets the master know that
the latest byte of information was received. The acknowl-
edge-related clock pulse is generated by the master. The
transmitter master releases the SDA line (HIGH) during
the acknowledge clock pulse. The slave receiver must pull
down the SDA line during the acknowledge clock pulse
so that it remains stable LOW during the HIGH period of
this clock pulse.
When a slave receiver doesn’t acknowledge the slave
address (for example, it’s unable to receive because it’s
performing some real-time function), the data line must
be left HIGH by the slave. The master can then generate
a STOP command to abort the transfer.
If a slave receiver does acknowledge the slave address but,
some time later in the transfer cannot receive any more
data bytes, the master must again abort the transfer. This
is indicated by the slave generating the not acknowledge
on the ?rst byte to follow. The slave leaves the data line
HIGH and the master generates the STOP command. The
data line is also left high by the slave and master after a
slave has transmitted a byte of data to the master in a read
operation, but this is a not acknowledge that indicates that
the data transfer is successful.
Commands Supported
The LTC3447 supports only write byte commands to a
single register. During ACK bit periods, the LTC3447 will
pull the data line low to acknowledge the master device.
See Figure 7.
Data Transfer Timing for Write Commands
In order to help assure that bad data is not written into
the part, data from a write command is only stored after
a valid STOP command has been performed.
WRITE BYTE PROTOCOL
1
START
7
1100110
1
0
1
ACK
8
XXXXXXXX
1
ACK
1
STOP
SLAVE
WRITE
DATA
ADDRESS
I 2 C REGISTER DEFINITION
MSB
7
DISABLE
BURST
6
ENABLE
PGOOD
5
BUCK
DAC5
4
BUCK
DAC4
3
BUCK
DAC3
2
BUCK
DAC2
1
BUCK
DAC1
0
BUCK
DAC0
LSB
(DEFAULT = 0)
BLANKING (DEFAULT = 1) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0)
(DEFAULT = 0)
3447 F07
Figure 7. LTC3447’s Write I 2 C Protocol
3447f
10
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| LTC3448EDD | 功能描述:IC REG BUCK SYNC ADJ 0.6A 8DFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 产品培训模块:MIC23xxx HyperLight Load™ Regulators 标准包装:5,000 系列:HyperLight Load® 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.8V 输入电压:2.7 V ~ 5.5 V PWM 型:混合物 频率 - 开关:4MHz 电流 - 输出:2A 同步整流器:是 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-VFDFN 裸露焊盘，8-MLF? 包装:带卷 (TR) 供应商设备封装:8-MLF?（2x2） 产品目录页面:1094 (CN2011-ZH PDF) 其它名称:576-3303-2 |
| LTC3448EDD#PBF | 功能描述:IC REG BUCK SYNC ADJ 0.6A 8DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:2,500 系列:- 类型:升压（升压） 输出类型:可调式 输出数:1 输出电压:1.24 V ~ 30 V 输入电压:1.5 V ~ 12 V PWM 型:电流模式，混合 频率 - 开关:600kHz 电流 - 输出:500mA 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) 供应商设备封装:8-SOIC |
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