参数资料
型号: LTC3447EDD#TRPBF
厂商: Linear Technology
文件页数: 15/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.6A 10DFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.69 V ~ 2.05 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 1MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 10-DFN(3x3)
LTC3447
APPLICATIO S I FOR ATIO
? V OUT = 0 . 280 A ? 0 . 25 ? +
?=
Design Example
As a design example, assume the LTC3447 is used in a
?
?
1 ?
8 ( 1 MHz )( 4 . 7 μ F ) ?
single lithium-ion battery-powered cellular phone applica-
tion. The V IN will be operating from a maximum of 4.2V
down to about 2.7V. The normal load current requirement
is a maximum of 500mA at 1.4V, but most of the time it will
be in standby mode, requiring only 200μA at 1V. Ef?ciency
at both low and high load currents is important.
To ensure that the ripple currents and voltages do not
exceed desired expectations over the DAC output range,
calculations with maximum V IN and minimum V OUT should
be used. Note that either increasing the output voltage or
decreasing V IN will result in a decrease of ripple current
and voltage. Choosing a maximum ripple current, Δ I L , of
280mA, Equation 1 can be used to determine the size of
the inductor that should be used.
70 mV + 7 . 4 mV = 77 . 4 mV
Note that the majority of the ripple voltage is generated
by the capacitor’s ESR. Most ceramic capacitors will have
a typical ESR of 10m Ω or less. Selecting capacitors with
low ESRs will signi?cantly reduce the ripple voltage.
Ef?ciency can be improved by taking advantage of the
LT3447’s Burst Mode operation. When entering the standby
mode, ensure that the burst disable bit is set to 0 when
the output voltage DAC is updated. Likewise, when enter-
ing a heavy current load mode, ensure the burst disable
bit is set to 1 when the output voltage DAC is updated.
Figure 11 shows the advantage of utilizing the Burst Mode
function.
? 1 . 4 V ? 1 –
? = 3 . 3 μ H
L =
1
( 1 MHz )( 280 mA )
?
?
1 . 4 V ?
4 . 2 V ?
100
90
80
70
STBY
DAC(MAX)
DAC(MAX)
A 3.3μH inductor works well for this application. For best
ef?ciency choose a 640mA or greater inductor with less
than 0.2 Ω series resistance.
60
50
40
30
DAC(MIN)
NORMAL
20
C IN will require an RMS current of at least 0.25A, approxi-
10
DAC(MIN)
BURST
PSK
mately I LOAD(MAX) /2, overtemperature (see Equation 2). For
C OUT , selecting a 4.7μF capacitor with an ESR of 0.25 Ω
0
0.1
1
10 100
LOAD CURRENT (mA)
1000
3447 F11
yields the following ripple voltage using Equation 3.
PACKAGE DESCRIPTIO
DD Package
Figure 11. Ef?ciency vs Load Current ( V IN = 4.2V)
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.675 ± 0.05
R = 0.115
TYP
6
10
0.38 ± 0.10
3.50 ± 0.05 1.65 ± 0.05
2.15 ± 0.05 (2 SIDES)
PACKAGE
PIN 1
TOP MARK
3.00 ± 0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
OUTLINE
(SEE NOTE 6)
(DD10) DFN 1103
0.25 ± 0.05
0.50
0.200 REF
0.75 ± 0.05
5
1
0.25 ± 0.05
0.50 BSC
BSC
2.38 ± 0.10
2.38 ± 0.05
(2 SIDES)
0.00 – 0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD
FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3447f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
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