参数资料
型号: LTC3447EDD#TRPBF
厂商: Linear Technology
文件页数: 14/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.6A 10DFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.69 V ~ 2.05 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 1MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 10-DFN(3x3)
LTC3447
APPLICATIO S I FOR ATIO
junction temperature of the part. The temperature rise
is given by:
T R = θ JA ? P D
where P D is the power dissipated by the regulator and
θ JA is the thermal resistance from the junction of the die
to the temperature.
The junction temperature, T J , is given by:
T J = T A + T R
possible? This capacitor provides the AC current to the
internal power MOSFETs.
5. Keep the switching node, SW, away from the sensitive
V OUT and FB nodes.
6. Keep the (–) plates of C IN and C OUT as close as pos-
sible.
where T A is the ambient temperature.
As an example, consider the LTC3447 when using an input
voltage of 3.6V, an ambient temperature of 70°C, and a
buck load current of 500mA. From the typical performance
graph of switch resistance, the R DS(ON) of the P-channel
switch at 70°C is approximately 0.45 Ω . Therefore, power
dissipated by the part is:
P D = I LOAD2 ? R DS(ON) = 112.5mW
For the DFN-10 package, the θ JA is 43°C/W. Thus, the
junction temperature of the regulator is:
T J = 70°C + (0.1125)(43) = 74.8°C
which is well below the maximum junction temperature of
R1
R2
V OUT
GND
FB
PGOOD
V IN
GND PLANE
SDA
V CCD
SCL
RUN
SW
C2
150°C. Note that at higher supply voltages, the junction
V IN
C IN
L1
temperature is lower due to reduced switch resistance
(R DS(ON) ).
PC Board Layout Checklist
When laying out the printed circuit board, the following
GND PLANE
C OUT
VIA
TO
V OUT
3447 F09
checklist should be used to ensure proper operation of
the LTC3447. These items are also illustrated graphically
in Figures 9 and 10. Check the following in your layout:
Figure 9. LTC3447 Suggested Layout
1. The power traces, consisting of the GND trace, the
R1
V OUT
SDA
SW trace, and the V IN trace should be kept short, direct
and wide.
2. Does the V OUT pin connect directly to the output voltage
R2
GND
FB
V CCD
SCL
C2
reference? Ensure that there is no load current running
from the output voltage and the V OUT sense pin.
3. Does the FB pin connect directly to the feedback voltage
PGOOD
V IN
RUN
SW
reference? Ensure that there is no load current running
from the feedback reference voltage and the FB pin.
V IN
C IN
C OUT
L1
V OUT
4. Does the (+) plate of C IN connect to V IN as closely as
3447 F11
Figure 10. LTC3447 Layout Diagram
3447f
14
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