参数资料
型号: LTC3536EDD#PBF
厂商: Linear Technology
文件页数: 14/28页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC ADJ 12DFN
标准包装: 121
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 1.8 V ~ 5.5 V
输入电压: 1.8 V ~ 5.5 V
PWM 型: 电压模式,混合
频率 - 开关: 300kHz ~ 2MHz
电流 - 输出: 1A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 10-DFN(3x3)
LTC3536
APPLICATIONS INFORMATION
V OUT ? V IN – V OUT ?
? ?
? ?
? V (P-P)(BUCK) = 2
8 ? f ? L ? C OUT
I LOAD ? V OUT – V IN ?
f ? C OUT ? ?
? ?
? V (P-P)(BOOST) =
NeglectingthecapacitorESRandESL,thepeak-to-peak
output voltage ripple can be calculated by the following
formulas, where f is the frequency in MHz, C OUT is the
capacitance in μF and I LOAD is the output current in amps.
V IN
V OUT
Given that the output current is discontinuous in boost
mode, the ripple in this mode will generally be much larger
than the magnitude of the ripple in buck mode.
In addition to output voltage ripple generated across the
output capacitance, there is also output voltage ripple
produced across the internal resistance of the output
capacitor. The ESR-generated output voltage ripple is
proportional the series resistance of the output capacitor.
Input Capacitor Selection
The PV IN pin carries the full inductor current and provides
power to internal control circuits in the IC. To minimize
input voltage ripple and ensure proper operation of the IC,
a low ESR bypass capacitor with a value of at least 10μF
should be located as close to this pin as possible. The
traces connecting this capacitor to PV IN and the ground
plane should be made as short as possible. The SV IN pin
provides power to the internal circuitry. In every applica-
tion, the SV IN and PV IN must be connected together on
the PC Board.
Recommended Input and Output Capacitors
The capacitors used to filter the input and output of the
LTC3536 must have low ESR and must be rated to handle
the large AC currents generated by switching converters.
This is important to maintain proper functioning of the IC
and to reduce output voltage ripple.
The choice of capacitor technology is primarily dictated
by a trade-off between cost, size and leakage current.
Ceramic capacitors are often utilized in switching con-
verter applications due to their small size, low ESR and
low leakage currents. However, many ceramic capacitors
designed for power applications experience significant
loss in capacitance from their rated value with increased
DC bias voltages. For example, it is not uncommon for
a small surface mount ceramic capacitor to lose more
than 50% of its rated capacitance when operated near its
rated voltage. As a result, it is sometimes necessary to
use a larger value capacitance or a capacitor with a higher
voltage rating than required in order to actually realize the
intended capacitance at the full operating voltage. To ensure
that the intended capacitance is realized in the application
circuit, be sure to consult the capacitor vendor’s curve of
capacitance versus DC bias voltage.
The capacitors listed in Table 2 provide a sampling of small
surface mount ceramic capacitors that are well suited to
LTC3536 application circuits. All listed capacitors are either
X5R or X7R dielectric in order to ensure that capacitance
loss over temperature is minimized.
Table 2. Representative Bypass and Output Capacitors
VALUE VOLTAGE SIZE (mm)
PART NUMBER (μF) (V) L × W × H (FOOTPRINT)
AVX
12066D106K 10 6.3 3.2 × 1.6 × 0.5 (1206)
12066D226K 22 6.3 3.2 × 1.6 × 0.5 (1206)
12066D476K 47 6.3 3.2 × 1.6 × 0.5 (1206)
Kemet
C0603C106K9P 10 6.3 1.6 × 0.8 × 0.8 (0603)
C0805C226K9P 22 6.3 2.0 × 1.25 × 1.25 (0805)
C0805C476K9P 47 6.3 2.0 × 1.25 × 1.25 (0805)
Murata
GRM21 10 10 2.0 × 1.25 × 1.25 (0805)
GRM21 22 6.3 2.0 × 1.25 × 1.25 (0805)
TDK
C2102X5R0J 22 6.3 2.0 × 1.25 × 0.85 (0805)
C2102X5R0J 47 6.3 2.0 × 1.25 × 1.25 (0805)
Taiyo Yuden
JMK212BJ 22 6.3 2.0 × 1.25 × 0.85 (0805)
JMK212BJ 47 6.3 2.0 × 1.25 × 0.85 (0805)
Small-Signal Model
The LTC3536 uses a voltage mode control loop to maintain
regulation of the output voltage. An externally compen-
sated error amplifier drives the VC pin to generate the
appropriate duty cycle of the power switches. Use of an
external compensation network provides the flexibility for
optimization of closed-loop performance over the wide
3536fa
14
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