参数资料
型号: LTC3536EDD#PBF
厂商: Linear Technology
文件页数: 18/28页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC ADJ 12DFN
标准包装: 121
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 1.8 V ~ 5.5 V
输入电压: 1.8 V ~ 5.5 V
PWM 型: 电压模式,混合
频率 - 开关: 300kHz ~ 2MHz
电流 - 输出: 1A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 10-DFN(3x3)
LTC3536
APPLICATIONS INFORMATION
f POLE2 f POLE3
f ZERO1
? ? ? ? 1 + 2 π f
? ? 1 + 2 π f
V C(S) ZERO1 ZERO2 ?
= G EA
? ? ? ? 1 + 2 π f
s ? 1 +
2 π f POLE1
?
POLE2 ?
G EA =
f ZERO1 =
GAIN
–20dB/DEC
–20dB/DEC
90°
PHASE
–90°
f
3536 F08
f ZERO2
Figure 8. Type III Compensation Bode Plot
The transfer function of the compensated Type III error
amplifier from the input of the resistor divider to the output
of the error amplifier, VC, is:
? s ? ? s ?
V OUT(S) ? s ? ? s ?
?
The error amplifier gain is given by the following equation.
The simpler approximate value is sufficiently accurate in
most cases since C FB is typically much larger in value
than C POLE .
1 1
R TOP ( C FB + C POLE ) R TOP C FB
The pole and zero frequencies of the Type III compensation
network can be calculated from the following equations
where all frequencies are in Hz, resistances are in ohms,
and capacitances are in farads.
1
2 π R FB C FB
In most applications the compensation network is designed
so that the loop crossover frequency is above the resonant
frequency of the power stage, but sufficiently below the
boost mode right-half plane zero to minimize the additional
phase loss. Once the crossover frequency is decided upon,
the phase boost provided by the compensation network
is centered at that point in order to maximize the phase
margin. A larger separation in frequency between the
zeros and higher order poles will provide a higher peak
phase boost but may also increase the gain of the error
amplifier which can push out the loop crossover to a
higher frequency.
The Q of the power stage can have a significant influence
on the design of the compensation network because it
determines how rapidly the 180° of phase loss in the power
stage occurs. For very low values of series resistance, R S ,
the Q will be higher and the phase loss will occur sharply.
In such cases, the phase of the power stage will fall rapidly
to –180° above the resonant frequency and the total phase
margin must be provided by the compensation network.
However, with higher losses in the power stage (larger R S )
the Q factor will be lower and the phase loss will occur
more gradually. As a result, the power stage phase will
not be as close to –180° at the crossover frequency and
less phase boost is required of the compensation network.
The LTC3536 error amplifier is designed to have a fixed
maximum bandwidth in order to provide rejection of
switching noise to prevent it from interfering with the
control loop. From a frequency domain perspective, this
can be viewed as an additional single pole as illustrated
in Figure?9. The nominal frequency of this pole is 400kHz.
For typical loop crossover frequencies below about 40kHz
the phase contributed by this additional pole is usually
LTC3536
f ZERO2 =
1
2 π ( R TOP + R FF ) C FF
1
2 π R TOP C FF
0.6V
FB
VC
+
R FILT
C FILT
INTERNAL
VC
f POLE2 =
C FB + C POLE
2 π C FB C POLE R FB
1
2 π C POLE R FB
Figure 9. Internal Loop Filter
3536 F09
f POLE3 =
18
1
2 π C FF R FF
3536fa
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