参数资料
型号: LTC3536EDD#PBF
厂商: Linear Technology
文件页数: 20/28页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC ADJ 12DFN
标准包装: 121
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 1.8 V ~ 5.5 V
输入电压: 1.8 V ~ 5.5 V
PWM 型: 电压模式,混合
频率 - 开关: 300kHz ~ 2MHz
电流 - 输出: 1A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 10-DFN(3x3)
LTC3536
APPLICATIONS INFORMATION
? ? ( 2 π f C ) ( R TOP C FB ) ? ?
= 198pF ≈ 180pF
C FB
f Z = ? f C = ? ( ) = 5.4kHz
37.8kHz
R FB =
= 163k ? ≈ 162k ?
C POLE =
= 3.71pF ≈ 3.9pF
C FF =
= 34.9pF ≈ 33pF
occuratthesamefrequency,f Z ,andbothhigherorderpoles
(f POLE2 and f POLE3 ) occur at the common frequency, f P .
This is a good starting point for determining the compen-
sation network. However the Bode plot for the complete
loop should be checked overall operating conditions and
for variations in components values to ensure that suf-
ficient phase margin and gain margin exists in all cases.
A reasonable choice is to pick the frequency of the poles,
f P , to be about 50 times higher than the frequency of the
zeros, f Z , which provides a peak phase boost of approxi-
mately Φ MAX = 60° as was assumed previously. Next, the
phase boost must be centered so that the peak phase
occurs at the target crossover frequency. The frequency
of the maximum phase boost, f C , is the geometric mean
of the pole and zero:
f C = f P ? f Z = 50 ? f Z 2 = 7 ? f Z
Therefore, in order to center the phase boost given a factor
of 50 separation between the pole and zero frequencies,
the zeros should be located at one-seventh of the cross-
over frequency and the poles should be located at seven
times the crossover frequency as given by the following
equations:
1    1
7 7
f P = 7 ? f C = 7 ? ( 37.8kHz ) = 264.6kHz
This placement of the poles and zeros will yield a peak phase
boost of 60° that is centered at the crossover frequency,
f C . Next, in order to produce the desired target crossover
frequency, the gain of the compensation network at the
point of maximum phase boost, G CENTER , must be set to
+2dB. The gain of the compensated error amplifier at the
point of maximum phase gain is given by:
Assuming a multiple of 50 separation between the pole
frequencies and zero frequencies this can be simplified
to the following expression:
? 50 ?
G CENTER = 20 log ? ?
The first step in defining the compensation component
values is to pick a value for R TOP that provides an accept-
ably low quiescent current through the resistor divider.
A value of R TOP = 845k is a reasonable choice. Next, the
value of C FB can be found:
G CENTER = 2dB
50
2dB
2 π ? ( 37.8kHz ) ? 845k ? ? 10 20
The compensation poles can be set at 264.6kHz and the
zeros at 5.4kHz by using the expressions for the pole and
zero frequencies given in the previous section. Setting the
frequency of the first zero, f ZERO1 , to 5.4kHz results in the
following value for R FB :
1
2 π ? ( 180pF ) ? 5.4kHz
This leaves the free parameter, C POLE , to set the frequency
f POLE1 to the common pole frequency of 264.6kHz as given:
1
2 π ? ( 162k ? ) ? 264.6kHz
Next, C FF can be chosen to set the second zero, f ZERO2 , to
the common zero frequency of 5.4kHz.
1
2 π ? ( 845k ? ) ? 5.4kHz
2 π f P
? ( 2 π f ) 3 ( R TOP C FB ) ?
2 ?
R FF =
= 18.2k ?
G CENTER = 10log
? ?
? ?
? Z
Finally, the resistor value R FF can be chosen to place the
second pole at 264.6kHz:
1
2 π ? ( 33pF ) ? 264.6kHz
3536fa
20
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